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* commit '40fac1a66ccf61bdf3afb70c18a5db7791410b22': (220 commits)
  Revert "tee: optee: interrupt an RPC when supplicant has been killed"
  Revert "tee: optee: interrupt an RPC depend on shutdown flag"
  arm64: dts: rockchip: rv1126bp-evb-v14: Adjust the matching voltage
  media: rockchip: aiisp: delete one temp buffer to reduce memory
  media: rockchip: isp: mp output buf notice to aiisp
  media: rockchip: aiisp: modify for aiynr algo
  rtc: rockchip: add ready flag for rtc setting time
  soc: rockchip: cpuinfo: export chip unique id to userspace
  media: rockchip: vpss: offline mode support auto unite output
  drm/rockchip: vop2: Add "DIMMING_DATA" property for local dimming
  media: rockchip: isp: aiisp switch for offline mode
  media: rockchip: isp: aiisp switch for isp35
  media: rockchip: isp: support aiisp yuv mode
  input: touchscreen: gt1x: prefix global variables and functions with "gt1x_"
  MALI: valhall: add gpu mem sysfs entry
  drm/rockchip: Make the DRM panel as part of Rockchip DRM sub devices for panel loader protect
  drm/rockchip: Pass struct rockchip_drm_sub_dev for &rockchip_drm_sub_dev.loader_protect()
  pwm: rockchip: Add &rockchip_pwm_chip.oneshot_valid to indicate validity of configurations
  pwm: rockchip: Add comments for why to add delay before disabling the dclk for PWM v4
  input: touchscreen: hyn: reduce logs
  ...

Change-Id: I1b562efca0842173010b2506231d7200a5116e5a
This commit is contained in:
Tao Huang
2025-07-28 16:41:15 +08:00
parent bfa6f2f019 40fac1a66c
commit d4ae9d6ea7
600 changed files with 65145 additions and 38612 deletions
Download Patch File Download Diff File Expand all files Collapse all files

133
Documentation/ABI/testing/sysfs-device-mali
View File

@@ -1,15 +1,21 @@
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
/*
*
* (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2017-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation) and any use by you of this program is subject to the terms
* of such GNU licence.
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* A copy of the licence is included with the program) and can also be obtained
* from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
* Boston) MA 02110-1301) USA.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
@@ -34,16 +40,6 @@ Description:
driver, On reading it provides the current DVFS sampling period,
on writing a value we set the DVFS sampling period.
What: /sys/class/misc/mali%u/device/dummy_job_wa_info
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU that requires a GPU workaround
to execute the dummy fragment job on all shader cores to
workaround a hang issue.
Its a readonly attribute and on reading gives details on the
options used with the dummy workaround.
What: /sys/class/misc/mali%u/device/fw_timeout
Description:
This attribute is available only with mali platform
@@ -78,111 +74,6 @@ Description:
is supported or is powered down after suspending command
stream groups.
What: /sys/class/misc/mali%u/device/js_ctx_scheduling_mode
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. This attribute is used to set
context scheduling priority for a job slot.
On Reading it provides the currently set job slot context
priority.
Writing 0 to this attribute sets it to the mode were
higher priority atoms will be scheduled first, regardless of
the context they belong to. Newly-runnable higher priority atoms
can preempt lower priority atoms currently running on the GPU,
even if they belong to a different context.
Writing 1 to this attribute set it to the mode were the
highest-priority atom will be chosen from each context in turn
using a round-robin algorithm, so priority only has an effect
within the context an atom belongs to. Newly-runnable higher
priority atoms can preempt the lower priority atoms currently
running on the GPU, but only if they belong to the same context.
What: /sys/class/misc/mali%u/device/js_scheduling_period
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. Used to set the job scheduler
tick period in nano-seconds. The Job Scheduler determines the
jobs that are run on the GPU, and for how long, Job Scheduler
makes decisions at a regular time interval determined by value
in js_scheduling_period.
What: /sys/class/misc/mali%u/device/js_softstop_always
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. Soft-stops are disabled when
only a single context is present, this attribute is used to
enable soft-stop when only a single context is present can be
used for debug and unit-testing purposes.
What: /sys/class/misc/mali%u/device/js_timeouts
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. It used to set the soft stop
and hard stop times for the job scheduler.
Writing value 0 causes no change, or -1 to restore the
default timeout.
The format used to set js_timeouts is
"<soft_stop_ms> <soft_stop_ms_cl> <hard_stop_ms_ss>
<hard_stop_ms_cl> <hard_stop_ms_dumping> <reset_ms_ss>
<reset_ms_cl> <reset_ms_dumping>"
What: /sys/class/misc/mali%u/device/lp_mem_pool_max_size
Description:
This attribute is used to set the maximum number of large pages
memory pools that the driver can contain. Large pages are of
size 2MB. On read it displays all the max size of all memory
pools and can be used to modify each individual pools as well.
What: /sys/class/misc/mali%u/device/lp_mem_pool_size
Description:
This attribute is used to set the number of large memory pages
which should be populated, changing this value may cause
existing pages to be removed from the pool, or new pages to be
created and then added to the pool. On read it will provide
pool size for all available pools and we can modify individual
pool.
What: /sys/class/misc/mali%u/device/mem_pool_max_size
Description:
This attribute is used to set the maximum number of small pages
for memory pools that the driver can contain. Here small pages
are of size 4KB. On read it will display the max size for all
available pools and allows us to set max size of
individual pools.
What: /sys/class/misc/mali%u/device/mem_pool_size
Description:
This attribute is used to set the number of small memory pages
which should be populated, changing this value may cause
existing pages to be removed from the pool, or new pages to
be created and then added to the pool. On read it will provide
pool size for all available pools and we can modify individual
pool.
What: /sys/class/misc/mali%u/device/device/mempool/ctx_default_max_size
Description:
This attribute is used to set maximum memory pool size for
all the memory pool so that the maximum amount of free memory
that each pool can hold is identical.
What: /sys/class/misc/mali%u/device/device/mempool/lp_max_size
Description:
This attribute is used to set the maximum number of large pages
for all memory pools that the driver can contain.
Large pages are of size 2MB.
What: /sys/class/misc/mali%u/device/device/mempool/max_size
Description:
This attribute is used to set the maximum number of small pages
for all the memory pools that the driver can contain.
Here small pages are of size 4KB.
What: /sys/class/misc/mali%u/device/pm_poweroff
Description:
This attribute contains the current values, represented as the

18
Documentation/ABI/testing/sysfs-device-mali-coresight-source
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@@ -1,15 +1,21 @@
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
/*
*
* (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2017-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation) and any use by you of this program is subject to the terms
* of such GNU licence.
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* A copy of the licence is included with the program) and can also be obtained
* from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
* Boston) MA 02110-1301) USA.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/

257
Documentation/devicetree/bindings/arm/mali-valhall.txt Normal file
View File

@@ -0,0 +1,257 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2013-2024 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
* ARM Mali Midgard / Bifrost devices
Required properties:
- compatible : Should be mali<chip>, replacing digits with x from the back,
until malit<Major>xx, and it must end with one of: "arm,malit6xx" or
"arm,mali-midgard" or "arm,mali-bifrost"
- reg : Physical base address of the device and length of the register area.
- interrupts : Contains the three IRQ lines required by T-6xx devices
- interrupt-names : Contains the names of IRQ resources in the order they were
provided in the interrupts property. Must contain: "JOB, "MMU", "GPU".
Optional:
- clocks : One or more pairs of phandle to clock and clock specifier
for the Mali device. The order is important: the first clock
shall correspond to the "clk_mali" source. Other clocks are optional
and, if present, they shall correspond to domains like "shadercores",
which is available for all GPUs, or "coregroup" and "neuralengines"
which are available for newer GPUs. Also notice that the "neuralengines"
clock domain, if present, doesn't expect a corresponding regulator.
- clock-names : Shall be set to values like: "clk_mali", "shadercores", "coregroup",
"neuralengines". Only the first one is mandatory. Most GPUs
support only the first two entries.
- mali-supply : Phandle to the top level regulator for the Mali device.
Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- mem-supply : Phandle to memory regulator for the Mali device. This is optional.
- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/mali-opp.txt
for details.
- quirks-gpu : Used to write to the JM_CONFIG or CSF_CONFIG register.
Should be used with care. Options passed here are used to override
certain default behavior. Note: This will override 'idvs-group-size'
field in devicetree and module param 'corestack_driver_control',
therefore if 'quirks-gpu' is used then 'idvs-group-size' and
'corestack_driver_control' value should be incorporated into 'quirks-gpu'.
- quirks-sc : Used to write to the SHADER_CONFIG register.
Should be used with care. Options passed here are used to override
certain default behavior.
- quirks-tiler : Used to write to the TILER_CONFIG register.
Should be used with care. Options passed here are used to
disable or override certain default behavior.
- quirks-mmu : Used to write to the L2_CONFIG register.
Should be used with care. Options passed here are used to
disable or override certain default behavior.
- power-model : Sets the power model parameters. Defined power models include:
"mali-simple-power-model", "mali-g51-power-model", "mali-g52-power-model",
"mali-g52_r1-power-model", "mali-g71-power-model", "mali-g72-power-model",
"mali-g76-power-model", "mali-g77-power-model", "mali-tnax-power-model",
"mali-tbex-power-model" and "mali-tbax-power-model".
- mali-simple-power-model: this model derives the GPU power usage based
on the GPU voltage scaled by the system temperature. Note: it was
designed for the Juno platform, and may not be suitable for others.
- compatible: Should be "arm,mali-simple-power-model"
- dynamic-coefficient: Coefficient, in pW/(Hz V^2), which is
multiplied by v^2*f to calculate the dynamic power consumption.
- static-coefficient: Coefficient, in uW/V^3, which is
multiplied by v^3 to calculate the static power consumption.
- ts: An array containing coefficients for the temperature
scaling factor. This is used to scale the static power by a
factor of tsf/1000000,
where tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0],
and T = temperature in degrees.
- thermal-zone: A string identifying the thermal zone used for
the GPU
- temp-poll-interval-ms: the interval at which the system
temperature is polled
- mali-g*-power-model(s): unless being stated otherwise, these models derive
the GPU power usage based on performance counters, so they are more
accurate.
- compatible: Should be, as examples, "arm,mali-g51-power-model" /
"arm,mali-g72-power-model".
- scale: the dynamic power calculated by the power model is
multiplied by a factor of 'scale'. This value should be
chosen to match a particular implementation.
- min_sample_cycles: Fall back to the simple power model if the
number of GPU cycles for a given counter dump is less than
'min_sample_cycles'. The default value of this should suffice.
* Note: when IPA is used, two separate power models (simple and counter-based)
are used at different points so care should be taken to configure
both power models in the device tree (specifically dynamic-coefficient,
static-coefficient and scale) to best match the platform.
- power-policy : Sets the GPU power policy at probe time. Available options are
"coarse_demand" and "always_on". If not set, then "coarse_demand" is used.
- system-coherency : Sets the coherency protocol to be used for coherent
accesses made from the GPU.
If not set then no coherency is used.
- 0 : ACE-Lite
- 1 : ACE
- 31 : No coherency
- ipa-model : Sets the IPA model to be used for power management. GPU probe will fail if the
model is not found in the registered models list. If no model is specified here,
a gpu-id based model is picked if available, otherwise the default model is used.
- mali-simple-power-model: Default model used on mali
- idvs-group-size : Override the IDVS group size value. Tasks are sent to
cores in groups of N + 1, so i.e. 0xF means 16 tasks.
Valid values are between 0 to 0x3F (including).
- l2-size : Override L2 cache size on GPU that supports it. Value should be larger than the minimum
size 1KiB and smaller than the maximum size. Maximum size is Hardware integration dependent.
The value passed should be of log2(Cache Size in Bytes).
For example for a 1KiB of cache size, 0xa should be passed.
- l2-hash : Override L2 hash function on GPU that supports it
- l2-hash-values : Override L2 hash function using provided hash values, on GPUs that supports it.
It is mutually exclusive with 'l2-hash'. Only one or the other must be
used in a supported GPU.
- arbiter-if : Phandle to the arbif platform device, used to provide KBASE with an interface
to the Arbiter. This is required when using arbitration; setting to a non-NULL
value will enable arbitration.
If arbitration is in use, then there should be no external GPU control.
When arbiter-if is in use then the following must not be:
- power-model (no IPA allowed with arbitration)
- #cooling-cells
- operating-points-v2 (no dvfs in kbase with arbitration)
- system-coherency with a value of 1 (no full coherency with arbitration)
- int-id-override: list of <ID Setting[7:0]> tuples defining the IDs needed to be
set and the setting coresponding to the SYSC_ALLOC register.
- propagate-bits: Used to write to L2_CONFIG.PBHA_HWU. This bitset establishes which
PBHA bits are propagated on the AXI bus.
- mma-wa-id: Sets a GPU MMU PBHA value to be used as NONCACHEABLE. GPU Page Table Entries
(PTEs) with this PBHA value set will have uncached transactions from the GPU.
Valid values are from 1 to 15. See mgm_update_gpu_pte() in
include/linux/memory_group_manager.h for the interface to configure the PTEs. Only
supported by arch 14.8.x and later GPUs.
Example for a Mali GPU with 1 clock and 1 regulator:
gpu@0xfc010000 {
compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
reg = <0xfc010000 0x4000>;
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&pclk_mali>;
clock-names = "clk_mali";
mali-supply = <&vdd_mali>;
operating-points-v2 = <&gpu_opp_table>;
power_model@0 {
compatible = "arm,mali-simple-power-model";
static-coefficient = <2427750>;
dynamic-coefficient = <4687>;
ts = <20000 2000 (-20) 2>;
thermal-zone = "gpu";
};
power_model@1 {
compatible = "arm,mali-g71-power-model";
scale = <5>;
};
idvs-group-size = <0x7>;
l2-size = /bits/ 8 <0x10>;
l2-hash = /bits/ 8 <0x04>; /* or l2-hash-values = <0x12345678 0x8765 0xAB>; */
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp@533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp@450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp@266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
Example for a Mali GPU with 2 clocks and 2 regulators:
gpu: gpu@6e000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x6e000000 0x0 0x200000>;
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&clk_mali 0>, <&clk_mali 1>;
clock-names = "clk_mali", "shadercores";
mali-supply = <&supply0_3v3>;
mem-supply = <&supply1_3v3>;
system-coherency = <31>;
operating-points-v2 = <&gpu_opp_table>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2", "operating-points-v2-mali";
opp@0 {
opp-hz = /bits/ 64 <50000000>;
opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>;
opp-microvolt = <820000>, <800000>;
opp-core-mask = /bits/ 64 <0xf>;
};
opp@1 {
opp-hz = /bits/ 64 <40000000>;
opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>;
opp-microvolt = <720000>, <700000>;
opp-core-mask = /bits/ 64 <0x7>;
};
opp@2 {
opp-hz = /bits/ 64 <30000000>;
opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>;
opp-microvolt = <620000>, <700000>;
opp-core-mask = /bits/ 64 <0x3>;
};
};
Example for a Mali GPU supporting PBHA configuration via DTB (default):
gpu@0xfc010000 {
...
pbha {
int-id-override = <2 0x32>, <9 0x05>, <16 0x32>;
propagate-bits = /bits/ 8 <0x03>;
mma-wa-id = <2>;
};
...
};

6
arch/arm/boot/dts/rockchip/Makefile
View File

@@ -58,11 +58,17 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1126b-evb1-v10-bt-sco.dtb \
rv1126b-evb1-v10-dual-4k.dtb \
rv1126b-evb1-v10-dv.dtb \
rv1126b-evb1-v10-fastboot-emmc.dtb \
rv1126b-evb1-v10-fastboot-spi-nand.dtb \
rv1126b-evb1-v10-fastboot-spi-nor.dtb \
rv1126b-evb1-v10-spi-nor.dtb \
rv1126b-evb1-v11.dtb \
rv1126b-evb1-v11-dual-4k.dtb \
rv1126b-evb2-v10.dtb \
rv1126b-evb2-v10-mcu-k350c4516t.dtb \
rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb \
rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb \
rv1126b-evb2-v10-tb-400w.dtb \
rv1126b-evb3-v10.dtb \
rv1126b-evb4-v10.dtb \
rv1126b-iotest-v10.dtb \

4
arch/arm/boot/dts/rockchip/rk3506g-demo-display-control.dts
View File

@@ -584,14 +584,12 @@
| RKPM_24M_OSC_DIS
| RKPM_32K_CLK
| RKPM_32K_SRC_RC
| RKPM_PWM0_CH0_CORE_PWREN
)
>;
rockchip,apios-suspend = <
(0
| RKPM_PWREN_CORE_GPIO0C1 | RKPM_PWREN_CORE_ACT_HIGH
| RKPM_PWREN_SLEEP_GPIO0B5 | RKPM_PWREN_SLEEP_ACT_HIGH
| RKPM_PWREN_SLEEP_GPIO0C1 | RKPM_PWREN_SLEEP_ACT_HIGH
)
>;
};

23
arch/arm/boot/dts/rockchip/rv1126b-evb1-v10-fastboot-emmc.dts Normal file
View File

@@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb1-v10-fastboot-emmc.dts"
/ {
model = "Rockchip RV1126B EVB1 V10 Fastboot Board";
compatible = "rockchip,rv1126b-evb1-v10-fastboot", "rockchip,rv1126b";
chosen {
bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K";
};
};
&ramdisk_r {
reg = <0x48c40000 (40 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x4b440000 (20 * 0x00100000)>;
};

23
arch/arm/boot/dts/rockchip/rv1126b-evb1-v10-fastboot-spi-nand.dts Normal file
View File

@@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb1-v10-fastboot-spi-nand.dts"
/ {
model = "Rockchip RV1126B EVB1 V10 Board";
compatible = "rockchip,rv1126b-evb1-v10-fastboot-spi-nand", "rockchip,rv1126b";
chosen {
bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K";
};
};
&ramdisk_r {
reg = <0x48c40000 (40 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x4b440000 (20 * 0x00100000)>;
};

23
arch/arm/boot/dts/rockchip/rv1126b-evb1-v10-fastboot-spi-nor.dts Normal file
View File

@@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb1-v10-fastboot-spi-nor.dts"
/ {
model = "Rockchip RV1126B EVB1 V10 Board";
compatible = "rockchip,rv1126b-evb1-v10-fastboot-spi-nand", "rockchip,rv1126b";
chosen {
bootargs = "loglevel=0 initcall_debug=0 earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 root=/dev/rd0 rootfstype=erofs rootflags=dax snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K";
};
};
&ramdisk_r {
reg = <0x48c40000 (20 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x4a040000 (10 * 0x00100000)>;
};

6
arch/arm/boot/dts/rockchip/rv1126b-evb1-v11-dual-4k.dts Normal file
View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb1-v11-dual-4k.dts"

6
arch/arm/boot/dts/rockchip/rv1126b-evb1-v11.dts Normal file
View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb1-v11.dts"

19
arch/arm/boot/dts/rockchip/rv1126b-evb2-v10-tb-400w.dts Normal file
View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb2-v10-tb-400w.dts"
/ {
model = "Rockchip RV1126B EVB2 V10 TB 400W Board";
compatible = "rockchip,rv1126b-evb2-v10-tb-400w", "rockchip,rv1126b";
};
&ramdisk_r {
reg = <0x48c40000 (30 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x4aa40000 (20 * 0x00100000)>;
};

72
arch/arm/configs/rv1126b-aov.config Normal file
View File

@@ -0,0 +1,72 @@
# CONFIG_ETHERNET is not set
CONFIG_EXTCON=y
CONFIG_INPUT=y
# CONFIG_MDIO_DEVICE is not set
# CONFIG_PHYLIB is not set
CONFIG_SND_SOC_RK_DSM=y
CONFIG_VIDEO_CAM_SLEEP_WAKEUP=y
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_HID is not set
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_ELAN is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
# CONFIG_INPUT_EVBUG is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_KEYBOARD=y
# CONFIG_INPUT_MATRIXKMAP is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_RC_CORE is not set
# CONFIG_RMI4_CORE is not set
# CONFIG_ROCKCHIP_REMOTECTL is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_SENSOR_DEVICE is not set
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
# CONFIG_SND_SOC_WM8962 is not set

1126
arch/arm/configs/rv1126b-cvr-fastboot.config Normal file
View File

File diff suppressed because it is too large Load Diff

1090
arch/arm/configs/rv1126b-cvr.config Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/configs/rv1126b-evb.config
View File

@@ -31,7 +31,6 @@ CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_RK_MEMBLOCK_PROCFS=y
CONFIG_ROCKCHIP_DEBUG=y
CONFIG_ROCKCHIP_OPP=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_SND_SOC_DUMMY_CODEC=y
@@ -843,6 +842,7 @@ CONFIG_TOUCHSCREEN_GT1X=y
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_HIMAX_CHIPSET is not set
# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set
# CONFIG_TOUCHSCREEN_HYN is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_ILITEK is not set
# CONFIG_TOUCHSCREEN_IMAGIS is not set

111
arch/arm/configs/rv1126b-fastboot.config
View File

@@ -1,24 +1,24 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_CRC16=m
CONFIG_CRC16=y
CONFIG_CRYPTO=y
CONFIG_DAX=y
CONFIG_ELF_CORE=y
CONFIG_EROFS_FS=y
# CONFIG_ETHERNET is not set
CONFIG_EXT4_FS=m
CONFIG_EXTCON=y
CONFIG_FILE_LOCKING=y
CONFIG_INPUT=y
CONFIG_JFFS2_FS=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_XZ is not set
CONFIG_LIBCRC32C=y
CONFIG_MAILBOX=y
# CONFIG_MDIO_DEVICE is not set
CONFIG_MMC=y
CONFIG_MSDOS_FS=m
CONFIG_MSDOS_PARTITION=y
CONFIG_MTD_BLOCK=m
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_PHYLIB is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_ROCKCHIP_DVBM=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_ROCKCHIP_MULTI_RGA=y
@@ -28,18 +28,26 @@ CONFIG_ROCKCHIP_THUNDER_BOOT=y
CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=m
# CONFIG_SLUB_SYSFS is not set
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_SIMPLE_CARD_UTILS=m
# CONFIG_SND_SIMPLE_CARD is not set
CONFIG_SND_SOC_DUMMY_CODEC=m
CONFIG_SND_SOC_RK_DSM=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_ASRC=m
CONFIG_SND_SOC_ROCKCHIP_PDM_V2=m
CONFIG_SND_SOC_ROCKCHIP_SAI=m
CONFIG_SND_SOC_RV1106=m
CONFIG_SPI=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_VFAT_FS=m
# CONFIG_VIDEO_RK_IRCUT is not set
CONFIG_VIDEO_ROCKCHIP_AIISP=y
CONFIG_VIDEO_ROCKCHIP_AVSP=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_VIDEO_ROCKCHIP_FEC=y
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_VPSS=y
CONFIG_VIDEO_SC200AI=y
CONFIG_VIDEO_SC450AI=y
CONFIG_VIDEO_SC850SL=y
# CONFIG_AD2S1200 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_AD2S90 is not set
@@ -109,16 +117,14 @@ CONFIG_VIDEO_SC450AI=y
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_MHU_V2 is not set
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_AS3935 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI088_ACCEL is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_CHARGER_BQ24190 is not set
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_AEGIS128 is not set
@@ -215,8 +221,11 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_ZSTD is not set
# CONFIG_DM9051 is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_ENC28J60 is not set
# CONFIG_ENCX24J600 is not set
# CONFIG_EROFS_FS_DEBUG is not set
# CONFIG_EROFS_FS_XATTR is not set
# CONFIG_EROFS_FS_ZIP is not set
@@ -224,6 +233,14 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
CONFIG_EXT4_USE_FOR_EXT2=y
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_EZX_PCAP is not set
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="cp936"
@@ -241,10 +258,27 @@ CONFIG_FS_MBCACHE=m
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# CONFIG_HI8435 is not set
# CONFIG_HID is not set
# CONFIG_I2C_HID_OF is not set
# CONFIG_I2C_HID_OF_ELAN is not set
# CONFIG_I2C_HID_OF_GOODIX is not set
# CONFIG_IIO_SSP_SENSORHUB is not set
CONFIG_INITCALL_ASYNC=y
# CONFIG_INITRAMFS_FORCE is not set
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_INPUT_EVBUG is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_KEYBOARD=y
# CONFIG_INPUT_MATRIXKMAP is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_ICM42670_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
@@ -264,6 +298,36 @@ CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_CYPRESS_SF is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KS8851 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_LMK04832 is not set
# CONFIG_LTC1660 is not set
@@ -271,8 +335,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_LTC2632 is not set
# CONFIG_LTC2688 is not set
# CONFIG_LTC2983 is not set
# CONFIG_MAILBOX_POLL_PERIOD_US is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_LZ4_DECOMPRESS=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
@@ -322,6 +385,7 @@ CONFIG_MMC_QUEUE_DEPTH=1
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MOXTET is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MSE102X is not set
CONFIG_MTD_BLKDEVS=m
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
@@ -357,11 +421,12 @@ CONFIG_MTD_SPI_NOR_WINBOND=y
# CONFIG_MTD_SPI_NOR_XMC is not set
# CONFIG_MTD_SPI_NOR_XTX is not set
# CONFIG_MTD_SST25L is not set
CONFIG_NET_VENDOR_ADI=y
# CONFIG_PI433 is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PWRSEQ_EMMC is not set
CONFIG_PWRSEQ_SIMPLE=y
# CONFIG_QCA7000_SPI is not set
# CONFIG_RC_CORE is not set
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_GZIP is not set
# CONFIG_RD_LZ4 is not set
@@ -371,16 +436,15 @@ CONFIG_PWRSEQ_SIMPLE=y
# CONFIG_RD_ZSTD is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_RMI4_CORE is not set
# CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST is not set
# CONFIG_ROCKCHIP_MBOX is not set
# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set
# CONFIG_ROCKCHIP_REMOTECTL is not set
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y
# CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE is not set
CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
@@ -399,15 +463,21 @@ CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_SCA3300 is not set
# CONFIG_SDIO_UART is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_SENSOR_DEVICE is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_SOC_ADAU1372_SPI is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_CS35L41_SPI is not set
# CONFIG_SND_SOC_CS35L45_SPI is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
@@ -415,6 +485,7 @@ CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=m
# CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
@@ -423,11 +494,13 @@ CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_SND_SOC_WM8731_SPI is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SPI is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AMD is not set
# CONFIG_SPI_AX88796C is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set

1
arch/arm/configs/rv1126b-ipc.config
View File

@@ -4,7 +4,6 @@ CONFIG_MSDOS_PARTITION=y
CONFIG_MTD_BLOCK=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_ROCKCHIP_OPP=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_SPI=y
CONFIG_VFAT_FS=y

268
arch/arm/configs/rv1126b-nand.config
View File

@@ -1,6 +1,81 @@
CONFIG_CRC16=y
CONFIG_CRYPTO=y
CONFIG_MTD_UBI=y
CONFIG_SPI=y
# CONFIG_AD2S1200 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_AD2S90 is not set
# CONFIG_AD3552R is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5766 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7280 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7293 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD74413R is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7816 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD8366 is not set
# CONFIG_AD8801 is not set
# CONFIG_AD9523 is not set
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# CONFIG_ADA4250 is not set
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_ADMV1013 is not set
# CONFIG_ADMV4420 is not set
# CONFIG_ADRF6780 is not set
# CONFIG_ADXL313_SPI is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL355_SPI is not set
# CONFIG_ADXL367_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AS3935 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI088_ACCEL is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_CRYPTO_842 is not set
CONFIG_CRYPTO_ACOMP2=y
# CONFIG_CRYPTO_ADIANTUM is not set
@@ -103,14 +178,204 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_ZSTD is not set
# CONFIG_DM9051 is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_ENC28J60 is not set
# CONFIG_ENCX24J600 is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_FXLS8962AF_SPI is not set
# CONFIG_FXOS8700_SPI is not set
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# CONFIG_HI8435 is not set
# CONFIG_IIO_SSP_SENSORHUB is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_ICM42670_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_KS8851 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_LMK04832 is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2632 is not set
# CONFIG_LTC2688 is not set
# CONFIG_LTC2983 is not set
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX11205 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX31856 is not set
# CONFIG_MAX31865 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3911 is not set
# CONFIG_MCP41010 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4922 is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_MFD_RK806_SPI is not set
# CONFIG_MFD_RSMU_SPI is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MOXTET is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MSE102X is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
CONFIG_MTD_NAND_BBT_USING_FLASH=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NAND_ATO=y
CONFIG_MTD_SPI_NAND_BIWIN=y
CONFIG_MTD_SPI_NAND_DEVICE_AUTOSELECT=y
CONFIG_MTD_SPI_NAND_DOSILICON=y
CONFIG_MTD_SPI_NAND_ESMT=y
CONFIG_MTD_SPI_NAND_ETRON=y
CONFIG_MTD_SPI_NAND_FMSH=y
CONFIG_MTD_SPI_NAND_FORESEE=y
CONFIG_MTD_SPI_NAND_GIGADEVICE=y
CONFIG_MTD_SPI_NAND_GSTO=y
CONFIG_MTD_SPI_NAND_HIKSEMI=y
CONFIG_MTD_SPI_NAND_HYF=y
CONFIG_MTD_SPI_NAND_JSC=y
CONFIG_MTD_SPI_NAND_MACRONIX=y
CONFIG_MTD_SPI_NAND_MICRON=y
CONFIG_MTD_SPI_NAND_PARAGON=y
CONFIG_MTD_SPI_NAND_SILICONGO=y
CONFIG_MTD_SPI_NAND_SKYHIGH=y
CONFIG_MTD_SPI_NAND_TOSHIBA=y
CONFIG_MTD_SPI_NAND_UNIM=y
CONFIG_MTD_SPI_NAND_WINBOND=y
CONFIG_MTD_SPI_NAND_XINCUN=y
CONFIG_MTD_SPI_NAND_XTX=y
CONFIG_MTD_SPI_NAND_ZBIT=y
# CONFIG_MTD_SPI_NOR is not set
# CONFIG_MTD_SST25L is not set
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_NET_VENDOR_ADI is not set
# CONFIG_PI433 is not set
# CONFIG_QCA7000_SPI is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_MCP795 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SCA3300 is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SGL_ALLOC=y
# CONFIG_SND_SOC_ADAU1372_SPI is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_CS35L41_SPI is not set
# CONFIG_SND_SOC_CS35L45_SPI is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
# CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_WM8731_SPI is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SPI is not set
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AMD is not set
# CONFIG_SPI_AX88796C is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_CADENCE_XSPI is not set
# CONFIG_SPI_DEBUG is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_MUX is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_ROCKCHIP is not set
# CONFIG_SPI_ROCKCHIP_FLEXBUS_FSPI is not set
# CONFIG_SPI_ROCKCHIP_FLEXBUS_SPI is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_ROCKCHIP_SLAVE is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_TI_TSC2046 is not set
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
@@ -120,6 +385,9 @@ CONFIG_UBIFS_FS_SECURITY=y
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_ZLIB=y
# CONFIG_UBIFS_FS_ZSTD is not set
# CONFIG_VIDEO_GS1662 is not set
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
# CONFIG_VIDEO_S5C73M3 is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
# CONFIG_ZRAM is not set

35
arch/arm/configs/rv1126b-rndis.config
View File

@@ -1,5 +1,6 @@
CONFIG_CONFIGFS_FS=y
CONFIG_CONFIGFS_FS=m
CONFIG_EXTCON=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_USB_SUPPORT=y
CONFIG_VIDEOBUF2_DMA_SG=m
# CONFIG_APPLE_MFI_FASTCHARGE is not set
@@ -12,6 +13,7 @@ CONFIG_VIDEOBUF2_DMA_SG=m
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_HISI_HIKEY_USB is not set
# CONFIG_I2C_CP2615 is not set
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
@@ -55,13 +57,13 @@ CONFIG_USB_CONFIGFS=m
# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
# CONFIG_USB_CONFIGFS_EEM is not set
CONFIG_USB_CONFIGFS_F_FS=y
# CONFIG_USB_CONFIGFS_F_HID is not set
CONFIG_USB_CONFIGFS_F_HID=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
# CONFIG_USB_CONFIGFS_F_MIDI is not set
# CONFIG_USB_CONFIGFS_F_PRINTER is not set
# CONFIG_USB_CONFIGFS_F_UAC1 is not set
CONFIG_USB_CONFIGFS_F_UAC1=y
# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
# CONFIG_USB_CONFIGFS_F_UAC2 is not set
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_UVC=y
# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
# CONFIG_USB_CONFIGFS_NCM is not set
@@ -76,12 +78,16 @@ CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DUMMY_HCD is not set
# CONFIG_USB_DWC2 is not set
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_DUAL_ROLE is not set
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_DUAL_ROLE=y
# CONFIG_USB_DWC3_GADGET is not set
# CONFIG_USB_DWC3_HOST is not set
CONFIG_USB_DWC3_OF_SIMPLE=m
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_EHCI_HCD_PLATFORM=m
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_EMI62 is not set
@@ -94,7 +100,10 @@ CONFIG_USB_DWC3_OF_SIMPLE=m
# CONFIG_USB_FUNCTIONFS is not set
# CONFIG_USB_FUSB300 is not set
CONFIG_USB_F_FS=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_GADGET=m
# CONFIG_USB_GADGETFS is not set
@@ -138,7 +147,8 @@ CONFIG_USB_LIBCOMPOSITE=m
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_USB_OHCI_HCD is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
# CONFIG_USB_ONBOARD_HUB is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
@@ -149,9 +159,10 @@ CONFIG_USB_LIBCOMPOSITE=m
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_RAW_GADGET is not set
# CONFIG_USB_ROLE_SWITCH is not set
CONFIG_USB_ROLE_SWITCH=m
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_TEST is not set
@@ -159,9 +170,13 @@ CONFIG_USB_LIBCOMPOSITE=m
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_ULPI is not set
# CONFIG_USB_ULPI_BUS is not set
CONFIG_USB_U_AUDIO=m
CONFIG_USB_U_ETHER=m
# CONFIG_USB_WDM is not set
# CONFIG_USB_XHCI_HCD is not set
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_HCD=m
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=m
# CONFIG_USB_YUREX is not set
# CONFIG_USB_ZERO is not set
# CONFIG_XILLYUSB is not set

464
arch/arm/configs/rv1126b-tb.config Normal file
View File

@@ -0,0 +1,464 @@
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CRYPTO=y
CONFIG_DAX=y
CONFIG_EROFS_FS=y
# CONFIG_ETHERNET is not set
CONFIG_JFFS2_FS=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_XZ is not set
CONFIG_LIBCRC32C=y
CONFIG_MAILBOX=y
# CONFIG_MDIO_DEVICE is not set
CONFIG_MMC=y
CONFIG_MTD_BLOCK=y
# CONFIG_PHYLIB is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_ROCKCHIP_DVBM=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RAMDISK=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_RKNPU=y
CONFIG_ROCKCHIP_THUNDER_BOOT=y
CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
# CONFIG_SLUB_SYSFS is not set
CONFIG_SPI=y
CONFIG_VIDEO_ROCKCHIP_AIISP=y
CONFIG_VIDEO_ROCKCHIP_AVSP=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_VPSS=y
CONFIG_VIDEO_SC200AI=y
CONFIG_VIDEO_SC450AI=y
# CONFIG_AD2S1200 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_AD2S90 is not set
# CONFIG_AD3552R is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5766 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7280 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7293 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD74413R is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7816 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD8366 is not set
# CONFIG_AD8801 is not set
# CONFIG_AD9523 is not set
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# CONFIG_ADA4250 is not set
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_ADMV1013 is not set
# CONFIG_ADMV4420 is not set
# CONFIG_ADRF6780 is not set
# CONFIG_ADXL313_SPI is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL355_SPI is not set
# CONFIG_ADXL367_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_MHU_V2 is not set
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_AS3935 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI088_ACCEL is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_AES_ARM is not set
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_ARIA is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_BLAKE2B is not set
# CONFIG_CRYPTO_BLAKE2S_ARM is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_CHACHA20_NEON is not set
# CONFIG_CRYPTO_CMAC is not set
# CONFIG_CRYPTO_CRC32 is not set
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_CURVE25519 is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_DH is not set
# CONFIG_CRYPTO_DRBG_MENU is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_ECDSA is not set
# CONFIG_CRYPTO_ECHAINIV is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_ESSIV is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_GHASH is not set
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
# CONFIG_CRYPTO_HCTR2 is not set
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_CRYPTO_JITTERENTROPY is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_LIB_UTILS=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_MANAGER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_PCRYPT is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_POLY1305_ARM is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RSA is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA1_ARM is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA256_ARM is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SHA512_ARM is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_SM3_GENERIC is not set
# CONFIG_CRYPTO_SM4_GENERIC is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_VMAC is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_ZSTD is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EROFS_FS_DEBUG is not set
# CONFIG_EROFS_FS_XATTR is not set
# CONFIG_EROFS_FS_ZIP is not set
# CONFIG_EZX_PCAP is not set
CONFIG_FS_DAX=y
CONFIG_FS_IOMAP=y
# CONFIG_FXLS8962AF_SPI is not set
# CONFIG_FXOS8700_SPI is not set
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# CONFIG_HI8435 is not set
# CONFIG_IIO_SSP_SENSORHUB is not set
CONFIG_INITCALL_ASYNC=y
# CONFIG_INITRAMFS_FORCE is not set
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_ICM42670_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_LMK04832 is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2632 is not set
# CONFIG_LTC2688 is not set
# CONFIG_LTC2983 is not set
CONFIG_MAILBOX_POLL_PERIOD_US=y
# CONFIG_MAILBOX_TEST is not set
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX11205 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX31856 is not set
# CONFIG_MAX31865 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3911 is not set
# CONFIG_MCP41010 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4922 is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_MFD_RK806_SPI is not set
# CONFIG_MFD_RSMU_SPI is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_MMC_CQHCI is not set
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_DW=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_ROCKCHIP=m
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_MTK is not set
CONFIG_MMC_QUEUE_DEPTH=1
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MOXTET is not set
# CONFIG_MPL115_SPI is not set
CONFIG_MTD_BLKDEVS=y
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MCHP48L640 is not set
# CONFIG_MTD_SPI_NAND is not set
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_ATMEL is not set
# CONFIG_MTD_SPI_NOR_BOYA is not set
# CONFIG_MTD_SPI_NOR_CATALYST is not set
# CONFIG_MTD_SPI_NOR_DEVICE_AUTOSELECT is not set
# CONFIG_MTD_SPI_NOR_DOSILICON is not set
# CONFIG_MTD_SPI_NOR_EON is not set
# CONFIG_MTD_SPI_NOR_ESMT is not set
# CONFIG_MTD_SPI_NOR_EVERSPIN is not set
# CONFIG_MTD_SPI_NOR_FMSH is not set
# CONFIG_MTD_SPI_NOR_FUJITSU is not set
CONFIG_MTD_SPI_NOR_GIGADEVICE=y
# CONFIG_MTD_SPI_NOR_INTEL is not set
# CONFIG_MTD_SPI_NOR_ISSI is not set
CONFIG_MTD_SPI_NOR_MACRONIX=y
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_NORMEM is not set
# CONFIG_MTD_SPI_NOR_PUYA is not set
# CONFIG_MTD_SPI_NOR_SPANSION is not set
# CONFIG_MTD_SPI_NOR_SST is not set
# CONFIG_MTD_SPI_NOR_STMICRO is not set
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPI_NOR_WINBOND=y
# CONFIG_MTD_SPI_NOR_XILINX is not set
# CONFIG_MTD_SPI_NOR_XMC is not set
CONFIG_MTD_SPI_NOR_XTX=y
# CONFIG_MTD_SST25L is not set
# CONFIG_PI433 is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PWRSEQ_EMMC is not set
CONFIG_PWRSEQ_SIMPLE=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_GZIP is not set
# CONFIG_RD_LZ4 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_ZSTD is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_ROCKCHIP_HW_DECOMPRESS_TEST is not set
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ROCKCHIP_MBOX_DEMO is not set
# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
# CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE is not set
# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y
CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE=y
CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RPMSG_ROCKCHIP_MBOX is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_MCP795 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SCA3300 is not set
# CONFIG_SDIO_UART is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SND_SOC_ADAU1372_SPI is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_CS35L41_SPI is not set
# CONFIG_SND_SOC_CS35L45_SPI is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
# CONFIG_SND_SOC_ROCKCHIP_SPI_CODEC is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set
# CONFIG_SND_SOC_WM8731_SPI is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SPI is not set
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AMD is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_CADENCE_XSPI is not set
# CONFIG_SPI_DEBUG is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_MUX is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_ROCKCHIP is not set
# CONFIG_SPI_ROCKCHIP_FLEXBUS_FSPI is not set
# CONFIG_SPI_ROCKCHIP_FLEXBUS_SPI is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_ROCKCHIP_SLAVE is not set
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS131E08 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_TI_TSC2046 is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_MAX3421_HCD is not set
# CONFIG_VIDEO_GS1662 is not set
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP=y
CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP=y
# CONFIG_VIDEO_S5C73M3 is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

5
arch/arm/configs/rv1126b-wakeup.config
View File

@@ -1,5 +0,0 @@
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_SND_JACK_INPUT_DEV=y

1
arch/arm/configs/rv1126b_defconfig
View File

@@ -175,6 +175,7 @@ CONFIG_ROCKCHIP_IOMMU=y
CONFIG_CPU_RV1126B=y
CONFIG_ROCKCHIP_AMP=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_OPP=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
CONFIG_FIQ_DEBUGGER=y

12
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566pro-evb2-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-dual-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dtb
@@ -297,12 +298,15 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test2-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test2-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test5-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-toybrick-d0-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20-amp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20-ufs.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v21.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v21-mcu.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576s-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576s-evb1-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576s-tablet-v10.dtb
@@ -377,14 +381,22 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-amp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-bt-sco.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-dual-4k.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-dv.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-emmc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nand.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nor.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-spi-nor.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-dual-4k.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-aov-dual-cam.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-mcu-k350c4516t.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-tb-400w.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-iotest-v10.dtb

36
arch/arm64/boot/dts/rockchip/rk3562-dictpen-test3-v20.dts
View File

@@ -919,6 +919,26 @@
power-supply = <&vcc3v3_lcd>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c5 {
@@ -1012,6 +1032,22 @@
<0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {

39
arch/arm64/boot/dts/rockchip/rk3562-evb.dtsi
View File

@@ -505,6 +505,29 @@
*/
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&jpegd {
@@ -526,6 +549,22 @@
<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};

39
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dtsi
View File

@@ -492,6 +492,29 @@
*/
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&pinctrl {
@@ -507,6 +530,22 @@
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};

39
arch/arm64/boot/dts/rockchip/rk3562-test1-ddr3-v10.dtsi
View File

@@ -227,6 +227,29 @@
power-supply = <&vcc3v3_lcd_n>;
};
&hynitron {
compatible = "hyn,3240";
reg = <0x5a>;
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
&mdio0 {
rgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -262,6 +285,22 @@
<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

39
arch/arm64/boot/dts/rockchip/rk3562-toybrick.dtsi
View File

@@ -293,6 +293,29 @@
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&mdio0 {
@@ -342,6 +365,22 @@
<0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {

5
arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtsi
View File

@@ -227,6 +227,11 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
status = "disabled";
power-supply = <&vcc3v3_lcd0_n>;
};
&hdmi {
status = "disabled";
};

4
arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi
View File

@@ -226,6 +226,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&i2c2 {
status = "okay";
pinctrl-names = "default";

4
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dts
View File

@@ -150,6 +150,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&hdmi {
status = "disabled";
};

4
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi
View File

@@ -405,6 +405,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&mipi_csi2 {
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi
View File

@@ -188,6 +188,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&i2c2 {
status = "okay";
pinctrl-0 = <&i2c2m1_xfer>;

4
arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi
View File

@@ -172,6 +172,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&i2c5 {
status = "disabled";
};

2
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts
View File

@@ -790,6 +790,8 @@
cy,vkeys_x = <1404>;
cy,vkeys_y = <1872>;
cy,max_x = <1872>;
cy,max_y = <1404>;
cy,revert_x = <0>;
cy,revert_y = <0>;
cy,xy_exchange = <0>;

19
arch/arm64/boot/dts/rockchip/rk3566pro-evb2-lp4x-v10.dts Normal file
View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3566pro-evb2-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"
/* vp0 for HDMI, vp1 for rgb */
&vp0 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | 1 << ROCKCHIP_VOP2_SMART0)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
};
&vp1 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | 1 << ROCKCHIP_VOP2_SMART1)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
};

623
arch/arm64/boot/dts/rockchip/rk3566pro-evb2-lp4x-v10.dtsi Normal file
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@@ -0,0 +1,623 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/rockchip_vop.h>
#include "rk3566pro.dtsi"
#include "rk3566-evb.dtsi"
/ {
model = "Rockchip RK3566PRO EVB2 LP4X V10 Board";
compatible = "rockchip,rk3566pro-evb2-lp4x-v10", "rockchip,rk3566pro", "rockchip,rk3566";
vcc_camera: vcc-camera-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&camera_pwr>;
regulator-name = "vcc_camera";
enable-active-high;
regulator-always-on;
regulator-boot-on;
};
vcc3v3_pcie: vcc3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
startup-delay-us = <5000>;
vin-supply = <&dc_12v>;
};
};
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&cpu0 {
cpu-supply = <&vdd_cpu_rk860>;
};
&bus_npu {
pvtm-supply = <&vdd_cpu_rk860>;
};
&combphy1_usq {
status = "okay";
};
&combphy2_psq {
status = "okay";
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
/*
* dphy0 only used for full mode,
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy0_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&gc8034_out>;
data-lanes = <1 2 3 4>;
};
mipi_in_ucam1: endpoint@2 {
reg = <2>;
remote-endpoint = <&ov5695_out>;
data-lanes = <1 2>;
};
mipi_in_ucam2: endpoint@3 {
reg = <3>;
remote-endpoint = <&gc5025_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy0_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp0_in_dphy0>;
};
};
};
};
&csi2_dphy1 {
status = "disabled";
/*
* dphy1 only used for split mode,
* can be used concurrently with dphy2
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy1_in: endpoint@1 {
reg = <1>;
//remote-endpoint = <&ov5695_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp0_in>;
};
};
};
};
&csi2_dphy2 {
status = "disabled";
/*
* dphy2 only used for split mode,
* can be used concurrently with dphy1
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_in: endpoint@1 {
reg = <1>;
//remote-endpoint = <&gc5025_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
/*
* video_phy0 needs to be enabled
* when dsi0 is enabled
*/
&dsi0 {
status = "okay";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "okay";
};
&dsi0_panel {
power-supply = <&vcc3v3_lcd0_n>;
reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd0_rst_gpio>;
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
tx_delay = <0x4f>;
rx_delay = <0x25>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&i2c0 {
vdd_cpu_rk860: rk8600@40{
compatible = "rockchip,rk8600";
reg = <0x40>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "rk860x-reg";
regulator-name = "vdd_cpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <2300>;
rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c2 {
status = "okay";
pinctrl-0 = <&i2c2m1_xfer>;
/* split mode: lane0/1 */
ov5695: ov5695@36 {
status = "okay";
compatible = "ovti,ov5695";
reg = <0x36>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clk>;
reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
/*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
ov5695_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
/* split mode: lane:2/3 */
gc5025: gc5025@37 {
status = "okay";
compatible = "galaxycore,gc5025";
reg = <0x37>;
clocks = <&pmucru CLK_WIFI>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&refclk_pins>;
reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
power-domains = <&power RK3568_PD_VI>;
/*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
gc5025_out: endpoint {
remote-endpoint = <&mipi_in_ucam2>;
data-lanes = <1 2>;
};
};
};
/* full mode: lane0-3 */
gc8034: gc8034@37 {
compatible = "galaxycore,gc8034";
status = "okay";
reg = <0x37>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clk>;
reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "RK-CMK-8M-2-v1";
rockchip,camera-module-lens-name = "CK8401";
port {
gc8034_out: endpoint {
remote-endpoint = <&dphy0_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&i2c4 {
/* i2c4 sda conflict with camera pwdn */
status = "disabled";
/*
* gc2145 needs to be disabled,
* when gmac1 is enabled;
* pinctrl conflicts;
*/
gc2145: gc2145@3c {
status = "disabled";
compatible = "galaxycore,gc2145";
reg = <0x3c>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
/* conflict with gmac1m1_rgmii_pins & cif_clk*/
pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>;
/*avdd-supply = <&vcc2v8_dvp>;*/
/*dovdd-supply = <&vcc1v8_dvp>;*/
/*dvdd-supply = <&vcc1v8_dvp>;*/
/*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/
pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CameraKing";
rockchip,camera-module-lens-name = "Largan";
port {
gc2145_out: endpoint {
remote-endpoint = <&dvp_in_bcam>;
};
};
};
};
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&mdio1 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
&gt1x {
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&mipi_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&dphy2_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
data-lanes = <1 2>;
};
};
};
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "disabled";
};
&pcie2x1 {
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
cam {
camera_pwr: camera-pwr {
rockchip,pins =
/* camera power en */
<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {
uart1_gpios: uart1-gpios {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd0 {
lcd0_rst_gpio: lcd0-rst-gpio {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd1 {
lcd1_rst_gpio: lcd1-rst-gpio {
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkcif {
status = "okay";
};
&rkcif_dvp {
status = "disabled";
port {
/* Parallel bus endpoint */
dvp_in_bcam: endpoint {
remote-endpoint = <&gc2145_out>;
bus-width = <8>;
vsync-active = <0>;
hsync-active = <1>;
};
};
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
data-lanes = <1 2>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy1_out>;
};
isp0_in_dphy0: endpoint@1 {
reg = <1>;
remote-endpoint = <&dphy0_out>;
};
};
};
&route_dsi0 {
//status = "disabled";
status = "okay";
connect = <&vp1_out_dsi0>;
};
&sdmmc2 {
status = "disabled";
};
&sdmmc1 {
max-frequency = <150000000>;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
sd-uhs-sdr104;
status = "okay";
};
&sdio_pwrseq {
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
};
&spdif_8ch {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spdifm1_tx>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&wireless_wlan {
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
};
&work_led {
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
};
&wireless_bluetooth {
compatible = "bluetooth-platdata";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;
uart_rts-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart1m0_rtsn>;
pinctrl-1 = <&uart1_gpios>;
BT,reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
BT,wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_host-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
status = "okay";
};

45
arch/arm64/boot/dts/rockchip/rk3566pro.dtsi Normal file
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@@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "rk356x.dtsi"
/ {
compatible = "rockchip,rk3566pro", "rockchip,rk3566";
};
&pipegrf {
compatible = "rockchip,rk3566-pipe-grf", "syscon";
};
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
clocks = <&cru PCLK_PIPE>;
pm_qos = <&qos_pcie2x1>,
<&qos_sata1>,
<&qos_sata2>,
<&qos_usb3_0>,
<&qos_usb3_1>;
#power-domain-cells = <0>;
};
};
&rkisp {
rockchip,iq-feature = /bits/ 64 <0x1BFBF7FE67FF>;
};
&usbdrd_dwc3 {
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
extcon = <&usb2phy0>;
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
};
/delete-node/ &route_edp;
/delete-node/ &vp0_out_edp;
/delete-node/ &vp1_out_edp;
/delete-node/ &edp;

7
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-ddr4-v10.dts
View File

@@ -15,6 +15,13 @@
goodix,irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd0_n>;
reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2dsi-dual-ddr4-v10.dts
View File

@@ -12,6 +12,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2gvi-ddr4-v10.dts
View File

@@ -16,6 +16,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-ddr4-v10.dts
View File

@@ -12,6 +12,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-hdmi2lvds-dual-ddr4-v10.dts
View File

@@ -16,6 +16,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

7
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2dsi-ddr4-v10.dts
View File

@@ -46,6 +46,13 @@
goodix,irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd0_n>;
reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2gvi-ddr4-v10.dts
View File

@@ -47,6 +47,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2hdmi-ddr4-v10.dts
View File

@@ -15,6 +15,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
assigned-clocks = <&pmucru CLK_WIFI>;
assigned-clock-rates = <24000000>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-ddr4-v10.dts
View File

@@ -47,6 +47,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

4
arch/arm64/boot/dts/rockchip/rk3568-evb-rk628-rgb2lvds-dual-ddr4-v10.dts
View File

@@ -48,6 +48,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2_rk628 {
panel-backlight = <&backlight>;
panel-power-supply = <&vcc3v3_lcd0_n>;

36
arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
View File

@@ -396,6 +396,7 @@
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
init-delay-ms = <10>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
width-mm = <68>;
@@ -730,6 +731,7 @@
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
init-delay-ms = <10>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
width-mm = <68>;
@@ -1378,6 +1380,24 @@
goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c5 {
@@ -1494,6 +1514,22 @@
<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {

4
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi
View File

@@ -263,6 +263,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&i2c4 {
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
View File

@@ -211,6 +211,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&i2c3 {
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi
View File

@@ -264,6 +264,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi
View File

@@ -111,6 +111,10 @@
power-supply = <&vcc3v3_lcd0_n>;
};
&hynitron {
power-supply = <&vcc3v3_lcd0_n>;
};
&i2c2 {
status = "okay";
pinctrl-names = "default";

35
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0-mipi-tx0.dtsi
View File

@@ -45,6 +45,25 @@
goodix,rst-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_LEVEL_LOW>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
status = "okay";
reg = <0x5a>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&pwm14{
@@ -72,5 +91,21 @@
<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>,
<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};

4
arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi
View File

@@ -44,6 +44,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&combphy0_us {
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi
View File

@@ -49,6 +49,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c0 {
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi
View File

@@ -49,6 +49,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c0 {
status = "okay";

6
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@@ -220,8 +220,10 @@
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
nvmem-cell-names = "id", "cpu-version", "cpu-code";
nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>,
<&specification_serial_number>, <&remark_spec_serial_number>;
nvmem-cell-names = "id", "cpu-version", "cpu-code",
"specification_serial_number", "remark_spec_serial_number";
};
display_subsystem: display-subsystem {

36
arch/arm64/boot/dts/rockchip/rk3576-evb.dtsi
View File

@@ -270,6 +270,7 @@
reset-delay-ms = <10>;
enable-delay-ms = <10>;
prepare-delay-ms = <10>;
init-delay-ms = <10>;
unprepare-delay-ms = <10>;
disable-delay-ms = <60>;
width-mm = <68>;
@@ -627,6 +628,25 @@
goodix,rst-gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_LOW>;
};
hynitron: hynitron@5a {
status = "disabled";
compatible = "hyn,3240";
reg = <0x5a>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c2 {
@@ -683,6 +703,22 @@
<0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {

4
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-dv.dts
View File

@@ -163,6 +163,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c2 {
status = "okay";
/delete-node/ husb311@4e;

5
arch/arm64/boot/dts/rockchip/rk3576-evb1.dtsi
View File

@@ -312,6 +312,11 @@
status = "okay";
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd_n>;
};
&i2c2 {
status = "okay";

2
arch/arm64/boot/dts/rockchip/rk3576-evb2.dtsi
View File

@@ -10,6 +10,7 @@
/delete-node/ &leds;
/delete-node/ &gt1x;
/delete-node/ &hynitron;
/ {
es8388_sound: es8388-sound {
@@ -570,4 +571,3 @@
wifi_chip_type = "ap6398s";
status = "okay";
};

5
arch/arm64/boot/dts/rockchip/rk3576-industry-evb.dtsi
View File

@@ -131,6 +131,11 @@
status = "okay";
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd_n>;
};
&i2c3 {
status = "okay";
pinctrl-names = "default";

35
arch/arm64/boot/dts/rockchip/rk3576-industry.dtsi
View File

@@ -585,6 +585,25 @@
goodix,rst-gpio = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio2 RK_PA4 IRQ_TYPE_LEVEL_LOW>;
};
hynitron: hynitron@5a {
status = "disabled";
compatible = "hyn,3240";
reg = <0x5a>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&iep {
@@ -632,6 +651,22 @@
<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};

7
arch/arm64/boot/dts/rockchip/rk3576-iotest.dtsi
View File

@@ -64,7 +64,7 @@
regulator-name = "vcc3v3_lcd0_n";
regulator-boot-on;
enable-active-high;
gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc_3v3_s0>;
};
@@ -128,6 +128,11 @@
status = "okay";
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd_n>;
};
&route_hdmi {
status = "disabled";
connect = <&vp0_out_hdmi>;

2
arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi
View File

@@ -5482,7 +5482,7 @@
pmic_pins: pmic-pins {
rockchip,pins =
/* pmic_int */
<0 RK_PA6 9 &pcfg_pull_up>,
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
/* pmic_sleep */
<0 RK_PA4 9 &pcfg_pull_none>;
};

5
arch/arm64/boot/dts/rockchip/rk3576-test1.dtsi
View File

@@ -281,6 +281,11 @@
status = "okay";
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd_n>;
};
&i2c0 {
status = "okay";

173
arch/arm64/boot/dts/rockchip/rk3576-test2-cam-dcphy0.dtsi Normal file
View File

@@ -0,0 +1,173 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam5: endpoint@6 {
reg = <6>;
remote-endpoint = <&ov50c40_out>;
data-lanes = <1 2 3>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c8 {
status = "okay";
pinctrl-0 = <&i2c8m3_xfer>;
aw8601: aw8601@c {
compatible = "awinic,aw8601";
status = "okay";
reg = <0x0c>;
rockchip,vcm-start-current = <56>;
rockchip,vcm-rated-current = <96>;
rockchip,vcm-step-mode = <4>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
ov50c40: ov50c40@36 {
compatible = "ovti,ov50c40";
status = "okay";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M0>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0m0_clk0>;
power-domains = <&power RK3576_PD_VI>;
avdd-supply = <&vcc_mipicsi0>;
reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "HZGA06";
rockchip,camera-module-lens-name = "ZE0082C1";
eeprom-ctrl = <&otp_eeprom>;
lens-focus = <&aw8601>;
port {
ov50c40_out: endpoint {
remote-endpoint = <&mipi_in_ucam5>;
bus-type = <1>;
data-lanes = <1 2 3>;
};
};
};
otp_eeprom: otp_eeprom@50 {
compatible = "rk,otp_eeprom";
status = "okay";
reg = <0x50>;
};
};
&mipidcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in0>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir0>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&rkisp_vir0_sditf {
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3576-test2-v10.dts
View File

@@ -9,6 +9,7 @@
#include "rk3576.dtsi"
#include "rk3576-test2.dtsi"
#include "rk3576-android.dtsi"
#include "rk3576-test2-cam-dcphy0.dtsi"
/ {
model = "Rockchip RK3576 TEST2 V10 Board";

18
arch/arm64/boot/dts/rockchip/rk3576-test2.dtsi
View File

@@ -154,6 +154,16 @@
pinctrl-names = "default";
pinctrl-0 = <&usb_otg0_pwren>;
};
vcc_mipicsi0: vcc-mipicsi0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipicsi0_pwr>;
regulator-name = "vcc_mipicsi0";
enable-active-high;
regulator-boot-on;
};
};
&backlight {
@@ -806,6 +816,14 @@
};
&pinctrl {
cam {
mipicsi0_pwr: mipicsi0-pwr {
rockchip,pins =
/* camera power en */
<3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_rst_gpio: lcd-rst-gpio {
rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;

5
arch/arm64/boot/dts/rockchip/rk3576-test5.dtsi
View File

@@ -163,6 +163,11 @@
power-supply = <&vcc3v3_lcd_n>;
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd_n>;
};
&i2c2 {
status = "okay";

195
arch/arm64/boot/dts/rockchip/rk3576-toybrick-cam-dcphy0.dtsi Normal file
View File

@@ -0,0 +1,195 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx415_out0>;
data-lanes = <1 2 3 4>;
};
mipi_in_ucam1: endpoint@2 {
reg = <2>;
remote-endpoint = <&ov50c40_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c9m2_xfer>;
imx415_dcphy0: imx415@1a {
compatible = "sony,imx415";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M0>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0m1_clk0>;
power-domains = <&power RK3576_PD_VI>;
power-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
imx415_out0: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
aw8601_0: aw8601@c {
compatible = "awinic,aw8601";
status = "okay";
reg = <0x0c>;
rockchip,vcm-start-current = <56>;
rockchip,vcm-rated-current = <96>;
rockchip,vcm-step-mode = <4>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
otp_eeprom_0: otp_eeprom@50 {
compatible = "rk,otp_eeprom";
status = "okay";
reg = <0x50>;
};
ov50c40_dcph0: ov50c40@36 {
compatible = "ovti,ov50c40";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M0>;
clock-names = "xvclk";
power-domains = <&power RK3576_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0m1_clk0>;
pwdn-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;// must be high at last
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;// must be high at last
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "HZGA06";
rockchip,camera-module-lens-name = "ZE0082C1-RK3568";
eeprom-ctrl = <&otp_eeprom_0>;
lens-focus = <&aw8601_0>;
port {
ov50c40_out0: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in0>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir0>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&rkisp_vir0_sditf {
status = "okay";
};

199
arch/arm64/boot/dts/rockchip/rk3576-toybrick-cam-dphy3.dtsi Normal file
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@@ -0,0 +1,199 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dphy1_hw {
status = "okay";
};
&csi2_dphy3 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam30: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx415_out1>;
data-lanes = <1 2 3 4>;
};
mipi_in_ucam31: endpoint@2 {
reg = <2>;
remote-endpoint = <&ov50c40_out1>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy3_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c6m1_xfer>;
imx415_dphy3: imx415@1a {
compatible = "sony,imx415";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M2>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&cam_clk2m1_clk2>;
power-domains = <&power RK3576_PD_VI>;
power-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
imx415_out1: endpoint {
remote-endpoint = <&mipi_in_ucam30>;
data-lanes = <1 2 3 4>;
};
};
};
aw8601_1: aw8601@c {
compatible = "awinic,aw8601";
status = "okay";
reg = <0x0c>;
rockchip,vcm-start-current = <56>;
rockchip,vcm-rated-current = <96>;
rockchip,vcm-step-mode = <4>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
otp_eeprom_1: otp_eeprom@50 {
compatible = "rk,otp_eeprom";
status = "okay";
reg = <0x50>;
};
ov50c40_dphy3: ov50c40@36 {
compatible = "ovti,ov50c40";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M2>;
clock-names = "xvclk";
power-domains = <&power RK3576_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cam_clk2m1_clk2>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_LOW>;// must be high at last
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;// must be high at last
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "HZGA06";
rockchip,camera-module-lens-name = "ZE0082C1-RK3568";
eeprom-ctrl = <&otp_eeprom_1>;
lens-focus = <&aw8601_1>;
port {
ov50c40_out1: endpoint {
remote-endpoint = <&mipi_in_ucam31>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi3_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy3_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi3_in>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds3 {
status = "okay";
port {
cif_mipi3_in: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif_mipi_lvds3_sditf {
status = "okay";
port {
mipi_lvds3_sditf: endpoint {
remote-endpoint = <&isp_vir1>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds3_sditf>;
};
};
};

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arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dtsi
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status = "disabled";
};
&hynitron {
status = "disabled";
power-supply = <&vcc3v3_lcd_n>;
};
&i2c0 {
s35390a: s35390a@30 {
compatible = "sii,s35390a";

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arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v21-maxim-max96712-dcphy0-ox03j10.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/media-bus-format.h>
/ {
max96712_dcphy0_osc: max96712-dcphy0-oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <25000000>;
clock-output-names = "max96712-dcphy0-osc";
};
max96712_dcphy0_vcc1v2: max96712-dcphy0-vcc1v2 {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_vcc1v2";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
startup-delay-us = <850>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dcphy0_vcc1v8: max96712-dcphy0-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_vcc1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <200>;
vin-supply = <&vcc_2v0_pldo_s3>;
};
max96712_dcphy0_pwdn_regulator: max96712-dcphy0-pwdn-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_pwdn";
gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dcphy0_pwdn>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
};
max96712_dcphy0_poc_regulator: max96712-dcphy0-poc-regulator {
compatible = "regulator-fixed";
regulator-name = "max96712_dcphy0_poc";
gpio = <&i2c7_nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
off-on-delay-us = <5000>;
vin-supply = <&dcphy0_vcc12v_buck1>;
};
};
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_dcphy0_in_max96712: endpoint@1 {
reg = <1>;
remote-endpoint = <&max96712_dcphy0_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c2 {
max96712_dcphy0: max96712@29 {
compatible = "maxim4c,max96712";
status = "okay";
reg = <0x29>;
clock-names = "xvclk";
clocks = <&max96712_dcphy0_osc 0>;
pinctrl-names = "default";
pinctrl-0 = <&max96712_dcphy0_errb>, <&max96712_dcphy0_lock>;
power-domains = <&power RK3576_PD_VI>;
rockchip,grf = <&sys_grf>;
vcc1v2-supply = <&max96712_dcphy0_vcc1v2>;
vcc1v8-supply = <&max96712_dcphy0_vcc1v8>;
pwdn-supply = <&max96712_dcphy0_pwdn_regulator>;
lock-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
max96712_dcphy0_out: endpoint {
remote-endpoint = <&mipi_dcphy0_in_max96712>;
data-lanes = <1 2 3 4>;
};
};
/* support mode config start */
support-mode-config {
status = "okay";
bus-format = <MEDIA_BUS_FMT_YUYV8_2X8>;
sensor-width = <1920>;
sensor-height = <1280>;
max-fps-numerator = <10000>;
max-fps-denominator = <300000>;
bpp = <16>;
link-freq-idx = <20>;
};
/* support mode config end */
/* serdes local device start */
serdes-local-device {
status = "okay";
/* GMSL LINK config start */
gmsl-links {
status = "okay";
link-vdd-ldo1-en = <1>;
link-vdd-ldo2-en = <1>;
// Link A: link-id = 0
gmsl-link-config-0 {
status = "okay";
link-id = <0>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam0>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
14 D1 03 00 00 // VGAHiGain
14 45 00 00 00 // Disable SSC
];
};
};
// Link B: link-id = 1
gmsl-link-config-1 {
status = "okay";
link-id = <1>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam1>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
15 D1 03 00 00 // VGAHiGain
15 45 00 00 00 // Disable SSC
];
};
};
// Link C: link-id = 2
gmsl-link-config-2 {
status = "okay";
link-id = <2>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam2>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
16 D1 03 00 00 // VGAHiGain
16 45 00 00 00 // Disable SSC
];
};
};
// Link D: link-id = 3
gmsl-link-config-3 {
status = "okay";
link-id = <3>; // Link ID: 0/1/2/3
link-type = <1>; // 0: GMSL1, 1: GMSL2
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
link-tx-rate = <0>; // 0: default for 187.5MBPS
link-remote-cam = <&max96712_dcphy0_cam3>; // remote camera
link-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
17 D1 03 00 00 // VGAHiGain
17 45 00 00 00 // Disable SSC
];
};
};
};
/* GMSL LINK config end */
/* VIDEO PIPE config start */
video-pipes {
status = "okay";
// Video Pipe 0
video-pipe-config-0 {
status = "okay";
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
];
};
};
// Video Pipe 1
video-pipe-config-1 {
status = "okay";
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
];
};
};
// Video Pipe 2
video-pipe-config-2 {
status = "okay";
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
];
};
};
// Video Pipe 3
video-pipe-config-3 {
status = "okay";
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
pipe-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
// For the following MSB 2 bits = VC, LSB 6 bits = DT
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
];
};
};
};
/* VIDEO PIPE config end */
/* MIPI TXPHY config start */
mipi-txphys {
status = "okay";
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
phy-force-clock-out = <1>; // 1: default for force clock out
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
// MIPI TXPHY A: phy-id = 0
mipi-txphy-config-0 {
status = "okay";
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0x4>;
vc-ext-en = <0>;
};
// MIPI TXPHY B: phy-id = 1
mipi-txphy-config-1 {
status = "okay";
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
phy-type = <0>; // 0: DPHY, 1: CPHY
auto-deskew = <0x80>;
data-lane-num = <4>;
data-lane-map = <0xe>;
vc-ext-en = <0>;
};
};
/* MIPI TXPHY config end */
/* local device extra init sequence */
extra-init-sequence {
status = "disabled";
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
// common init sequence such as fsync / gpio and so on
];
};
};
/* serdes local device end */
/* i2c-mux start */
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser0: max96717@51 {
compatible = "maxim,ser,max96717";
reg = <0x51>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0
03 02 10 00 00 // Improve CMU voltage performance to improve link robustness
14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation
14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode
03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz
00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output
00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled
02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup
02 BE 10 00 01 // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1
];
};
};
max96712_dcphy0_cam0: ox03j10@31 {
compatible = "maxim,ovti,ox03j10";
reg = <0x31>;
cam-i2c-addr-def = <0x36>;
cam-remote-ser = <&max96712_dcphy0_ser0>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam0_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser1: max96717@52 {
compatible = "maxim,ser,max96717";
reg = <0x52>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0
03 02 10 00 00 // Improve CMU voltage performance to improve link robustness
14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation
14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode
03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz
00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output
00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled
02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup
02 BE 10 00 01 // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1
];
};
};
max96712_dcphy0_cam1: ox03j10@32 {
compatible = "maxim,ovti,ox03j10";
reg = <0x32>;
cam-i2c-addr-def = <0x36>;
cam-remote-ser = <&max96712_dcphy0_ser1>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam1_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser2: max96717@53 {
compatible = "maxim,ser,max96717";
reg = <0x53>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0
03 02 10 00 00 // Improve CMU voltage performance to improve link robustness
14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation
14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode
03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz
00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output
00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled
02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup
02 BE 10 00 01 // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1
];
};
};
max96712_dcphy0_cam2: ox03j10@33 {
compatible = "maxim,ovti,ox03j10";
reg = <0x33>;
cam-i2c-addr-def = <0x36>;
cam-remote-ser = <&max96712_dcphy0_ser2>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam2_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
// Note: Serializer node defined before camera node
max96712_dcphy0_ser3: max96717@54 {
compatible = "maxim,ser,max96717";
reg = <0x54>;
ser-i2c-addr-def = <0x40>;
ser-init-sequence {
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
// reg_addr reg_val val_mask delay
init-sequence = [
02 BE 00 00 01 // MFP0 GPIO_OUT = 0: MFP0 output is driven to 0
03 02 10 00 00 // Improve CMU voltage performance to improve link robustness
14 17 00 00 00 // RLMS17 = 0x00: disable AGC/DFE adaptation
14 32 7f 00 00 // RLMS32 = 0x7F: change OSN loop mode
03 F0 59 00 00 // REFGEN_PREDEF_FREQ_ALT = 1: Alternative table, REFGEN_PREDEF_FREQ = 0x1: 24MHz
00 03 03 00 00 // RCLKSEL = 0x3: Reference PLL output
00 06 B1 00 01 // RCLKEN = 1: RCLK output is enabled
02 BF 40 00 00 // MFP0 PULL_UPDN_SEL = 1: Pullup
02 BE 10 00 01 // MFP0 GPIO_OUT = 1: MFP0 output is driven to 1
];
};
};
max96712_dcphy0_cam3: ox03j10@34 {
compatible = "maxim,ovti,ox03j10";
reg = <0x34>;
cam-i2c-addr-def = <0x36>;
cam-remote-ser = <&max96712_dcphy0_ser3>; // remote serializer
poc-supply = <&max96712_dcphy0_poc_regulator>;
rockchip,camera-module-index = <3>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
/* port config start */
port {
max96712_dcphy0_cam3_out: endpoint {
data-lanes = <1 2 3 4>;
};
};
/* port config end */
};
};
};
/* i2c-mux end */
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi0_in>;
};
};
};
};
&rkcif_mipi_lvds {
status = "okay";
/* parameters for do cif reset detecting:
* index0: monitor mode,
0 for idle,
1 for continue,
2 for trigger,
3 for hotplug (for nextchip)
* index1: the frame id to start timer,
min is 2
* index2: frame num of monitoring cycle
* index3: err time for keep monitoring
after finding out err (ms)
* index4: csi2 err reference val for resetting
*/
rockchip,cif-monitor = <3 2 1 1000 5>;
port {
cif_mipi0_in: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif {
status = "okay";
rockchip,android-usb-camerahal-enable;
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
max96712-dcphy0 {
max96712_dcphy0_pwdn: max96712-dcphy0-pwdn {
rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>;
};
max96712_dcphy0_errb: max96712-dcphy0-errb {
rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
max96712_dcphy0_lock: max96712-dcphy0-lock {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none_smt>;
};
};
};

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arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v21-mcu-io-expander.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
*/
#define MCU_PERI_5V_EN 0x01
#define MCU_CAM1_PWREN 0x02
#define MCU_CAM2_PWREN 0x03
#define DSP_CORE_PWR_EN 0x04
#define MCU_DSP_RST 0x05
#define FM_PWR_EN_MCU 0x06
#define ADC_PWDN_MCU 0x07
#define MCU_ADSP_VCC12V_EN 0x08
#define MCU_CAM3_PWREN 0x08
#define A2B_PWR_EN_MCU 0x09
#define MCU_RSTB_ETH 0x0a
#define MCU_DISB_ETH 0x0b
#define MUTE_AMP_MCU 0x0c
#define MCU_LCD1_SER_EN 0x0a
#define MCU_LCD2_SER_EN 0x0b
#define MCU_LCD3_SER_EN 0x0c
#define STANDBY_AMP_MCU 0x0d
#define MCU_CTRL_CluPWR 0x0e
#define MCU_LCD1_12V_EN 0x0f
#define MCU_LCD2_12V_EN 0x10
#define MCU_LCD3_12V_EN 0x11
#define MCU_CAM1_OUT1_EN 0x12
#define MCU_CAM1_OUT2_EN 0x13
#define MCU_CAM1_OUT3_EN 0x14
#define MCU_CAM1_OUT4_EN 0x15
#define MCU_CAM2_OUT1_EN 0x16
#define MCU_CAM2_OUT2_EN 0x17
#define MCU_CAM2_OUT3_EN 0x18
#define MCU_CAM2_OUT4_EN 0x19
#define MCU_CAM3_OUT1_EN 0x1a
#define MCU_CAM3_OUT2_EN 0x1b
#define MCU_CAM3_OUT3_EN 0x1c
#define MCU_CAM3_OUT4_EN 0x1d
#define MCU_USB3HOST_PWREN 0x1e
#define USB_OTG0_PWREN_H 0x1f
#define MCU_CTRL_VSYS 0x20
#define DSP_VCC1V8_PWR_EN 0x21
#define DSP_VCC3V3_PWR_EN 0x22
#define PERI_5V_PG 0x92
#define SYS4V_PG 0x93
#define FAULT_AMP3_MCU 0x92
#define FAULT_AMP4_MCU 0x93
#define MCU_DSP_FAULTB 0x94
#define ADC_INT_MCU 0x95
#define A2B_IRQ_MCU 0x96
#define ACC_DET 0x97
#define BACK_DET 0x98
#define MCU_CAM2_OUT1_DIAG 0x99
#define MCU_CAM2_OUT2_DIAG 0x9a
#define MCU_CAM2_OUT3_DIAG 0x9b
#define MCU_CAM2_OUT4_DIAG 0x9c
#define MCU_LCD1_PWR_DIAG 0x9d
#define MCU_LCD2_PWR_DIAG 0x9e
#define MCU_LCD3_PWR_DIAG 0x9f
/ {
gpio_mcu_rockchip: gpio-mcu-rockchip {
compatible = "rockchip,mcu-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
};
};
&spi4 {
compatible = "rockchip,spi-slave";
status = "okay";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi4m3_csn0 &spi4m3_pins>;
ready-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
slave@0 {
compatible = "rockchip,vehicle-spi";
status = "okay";
id = <0x0>;
reg = <0x0>;
spi-max-frequency = <1000000>;
spi-lsb-first;
pinctrl-names = "default";
pinctrl-0 = <&spi_irq_mcu>;
irq-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
slave-external-mcu {
spi_irq_mcu: spi-irq-mcu {
rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3576.dtsi"
#include "rk3576-vehicle-evb-v20.dtsi"
#include "rk3576-vehicle-evb-v21-mcu-io-expander.dtsi"
#include "rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi"
#include "rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03j10.dtsi"
#include "rk3576-vehicle-evb-v20-maxim-max96712-dphy3-sc233at.dtsi"
#include "rk3576-android.dtsi"
/delete-node/ &vcc5v0_host_usb30;
/ {
model = "Rockchip RK3576 VEHICLE EVB V21 Board";
compatible = "rockchip,rk3576-vehicle-evb-v21", "rockchip,rk3576";
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0x2ad40000 console=ttyFIQ0 rcupdate.rcu_expedited=1 rcu_nocbs=all spidev.bufsiz=131072";
};
vehicle_dummy: vehicle-dummy {
status = "okay";
compatible = "rockchip,vehicle-dummy-adc";
io-channels = <&saradc 4>, <&saradc 5>, <&saradc 6>;
io-channel-names = "gear", "turn_left", "turn_right";
};
vcc5v0_buck: vcc5v0-buck {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_buck_en>;
startup-delay-us = <2500>;
off-on-delay-us = <1500>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
cluster_power_buck: cluster_power-buck {
compatible = "regulator-fixed";
regulator-name = "cluster_power_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
//enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
vin-supply = <&vcc_1v8_s0>;
pinctrl-names = "default";
pinctrl-0 = <&cluster_buck_en>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
usb_otg_vcc5v_buck: usb_otg_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
//enable-active-high;
gpio = <&gpio_mcu_rockchip USB_OTG0_PWREN_H GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
usb_host_vcc5v_buck: usb_host_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "usb_host_vcc5v_buck";
//regulator-boot-on;
//regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_USB3HOST_PWREN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
lcd1_vcc12v_buck: lcd1_vcc12v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd1_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_LCD1_12V_EN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd2_vcc12v_buck: lcd2_vcc12v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd2_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_LCD2_12V_EN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd1_ser_vcc5v_buck: lcd1_ser_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd1_ser_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_LCD1_SER_EN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
lcd2_ser_vcc5v_buck: lcd2_ser_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd2_ser_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_LCD2_SER_EN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
adsp_vcc12v_buck: adsp_vcc12v-buck {
compatible = "regulator-fixed";
status = "disabled";
regulator-name = "adsp_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_ADSP_VCC12V_EN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd3_vcc12v_buck: lcd3_vcc12v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd3_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_LCD3_12V_EN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd3_vcc5v_buck: lcd3_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd3_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_LCD3_SER_EN GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck1: dcphy0_vcc12v-buck1 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck1";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM1_OUT1_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck2: dcphy0_vcc12v-buck2 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck2";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM1_OUT2_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck3: dcphy0_vcc12v-buck3 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck3";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM1_OUT3_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck4: dcphy0_vcc12v-buck4 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck4";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM1_OUT4_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck1: dphy0_vcc12v-buck1 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck1";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM2_OUT1_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck2: dphy0_vcc12v-buck2 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck2";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM2_OUT2_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck3: dphy0_vcc12v-buck3 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck3";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM2_OUT3_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck4: dphy0_vcc12v-buck4 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck4";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM2_OUT4_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck1: dphy3_vcc12v-buck1 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck1";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM3_OUT1_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck2: dphy3_vcc12v-buck2 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck2";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM3_OUT2_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck3: dphy3_vcc12v-buck3 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck3";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM3_OUT3_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck4: dphy3_vcc12v-buck4 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck4";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&gpio_mcu_rockchip MCU_CAM3_OUT4_EN GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
};
&dfi {
status = "disabled";
};
&dmc {
status = "disabled";
};
&gmac1 {
status = "disabled";
};
&hym8563 {
status = "disabled";
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m0_xfer>;
};
/*edp*/
&i2c3_max96752 {
use-reg-check-work;
vpower-supply = <&lcd1_vcc12v_buck>;
};
/*edp touch*/
&i2c3_himax {
himax,irq-gpio = <&gpio0 RK_PB6 IRQ_TYPE_EDGE_FALLING>;
};
/*dp*/
&i2c5_max96745 {
lock-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
};
&i2c5_ilitek {
interrupt-parent = <&gpio4>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
};
/*dp*/
&i2c5_max96752 {
use-reg-check-work;
vpower-supply = <&lcd2_vcc12v_buck>;
};
&i2c8_max96789 {
route-enable;
};
/*dsi*/
&i2c8_max96752 {
use-reg-check-work;
vpower-supply = <&lcd3_vcc12v_buck>;
};
&dp2lvds_backlight0 {
pwms = <&pwm2_8ch_7 0 25000 0>;
};
&edp2lvds_backlight0 {
pwms = <&pwm0_2ch_0 0 25000 0>;
};
&max96712_dphy0_poc_regulator {
gpio = <&gpio_mcu_rockchip MCU_CAM2_PWREN GPIO_ACTIVE_HIGH>;
};
/* edp->serdes->lvds_panel */
&pwm0_2ch_0 {
pinctrl-0 = <&pwm0m3_ch0>;
};
/* dp->serdes->lvds_panel */
&pwm2_8ch_7 {
pinctrl-0 = <&pwm2m3_ch7>;
};
&pinctrl {
touch {
//dsi-i2c8
touch_gpio_dsi: touch-gpio-dsi {
rockchip,pins =
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
//dp-i2c5
touch_gpio_dp: touch-gpio-dp {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
//edp0-i2c3
touch_gpio_edp: touch-gpio-edp {
rockchip,pins =
<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
vcc5v0-buck {
vcc5v0_buck_en: vcc5v0-buck-en {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
cluster-buck {
cluster_buck_en: cluster-buck-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&rkvpss {
status = "okay";
};
&rkvpss_mmu {
status = "okay";
};
&rkvpss_vir0 {
status = "okay";
};
&route_dsi {
status = "okay";
};
&sdmmc {
status = "disabled";
};
&ufs {
status = "disabled";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
//vbus-supply = <&usb_otg_vcc5v_buck>;
status = "okay";
};
&u2phy1_otg {
phy-supply = <&usb_host_vcc5v_buck>;
status = "okay";
};
&usbdp_phy {
maximum-speed = "high-speed";
status = "okay";
};
&usb_drd1_dwc3 {
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
status = "okay";
};

576
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v21.dts Normal file
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@@ -0,0 +1,576 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3576.dtsi"
#include "rk3576-vehicle-evb-v20.dtsi"
#include "rk3576-vehicle-evb-v20-nca9539-io-expander.dtsi"
#include "rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi"
#include "rk3576-vehicle-evb-v20-maxim-max96712-dphy0-ox03j10.dtsi"
#include "rk3576-vehicle-evb-v20-maxim-max96712-dphy3-sc233at.dtsi"
#include "rk3576-android.dtsi"
/delete-node/ &vcc5v0_host_usb30;
/ {
model = "Rockchip RK3576 VEHICLE EVB V21 Board";
compatible = "rockchip,rk3576-vehicle-evb-v21", "rockchip,rk3576";
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0x2ad40000 console=ttyFIQ0 rcupdate.rcu_expedited=1 rcu_nocbs=all spidev.bufsiz=131072";
};
vehicle_dummy: vehicle-dummy {
status = "okay";
compatible = "rockchip,vehicle-dummy-adc";
io-channels = <&saradc 4>, <&saradc 5>, <&saradc 6>;
io-channel-names = "gear", "turn_left", "turn_right";
};
vcc5v0_buck: vcc5v0-buck {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_buck_en>;
startup-delay-us = <2500>;
off-on-delay-us = <1500>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
cluster_power_buck: cluster_power-buck {
compatible = "regulator-fixed";
regulator-name = "cluster_power_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
//enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
vin-supply = <&vcc_1v8_s0>;
pinctrl-names = "default";
pinctrl-0 = <&cluster_buck_en>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
usb_otg_vcc5v_buck: usb_otg_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
//enable-active-high;
gpio = <&i2c0_nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
usb_host_vcc5v_buck: usb_host_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "usb_host_vcc5v_buck";
//regulator-boot-on;
//regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&i2c0_nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
lcd1_vcc12v_buck: lcd1_vcc12v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd1_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c0_nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd2_vcc12v_buck: lcd2_vcc12v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd2_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c0_nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd1_ser_vcc5v_buck: lcd1_ser_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd1_ser_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&i2c0_nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
lcd2_ser_vcc5v_buck: lcd2_ser_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd2_ser_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&i2c0_nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_buck>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <5000000>;
};
};
adsp_vcc12v_buck: adsp_vcc12v-buck {
compatible = "regulator-fixed";
regulator-name = "adsp_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c0_nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd3_vcc12v_buck: lcd3_vcc12v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd3_vcc12v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
lcd3_vcc5v_buck: lcd3_vcc5v-buck {
compatible = "regulator-fixed";
regulator-name = "lcd3_vcc5v_buck";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck1: dcphy0_vcc12v-buck1 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck1";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck2: dcphy0_vcc12v-buck2 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck2";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck3: dcphy0_vcc12v-buck3 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck3";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dcphy0_vcc12v_buck4: dcphy0_vcc12v-buck4 {
compatible = "regulator-fixed";
regulator-name = "dcphy0_vcc12v_buck4";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck1: dphy0_vcc12v-buck1 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck1";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 7 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck2: dphy0_vcc12v-buck2 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck2";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 8 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck3: dphy0_vcc12v-buck3 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck3";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 9 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy0_vcc12v_buck4: dphy0_vcc12v-buck4 {
compatible = "regulator-fixed";
regulator-name = "dphy0_vcc12v_buck4";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 10 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck1: dphy3_vcc12v-buck1 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck1";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 11 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck2: dphy3_vcc12v-buck2 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck2";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 12 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck3: dphy3_vcc12v-buck3 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck3";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 13 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
dphy3_vcc12v_buck4: dphy3_vcc12v-buck4 {
compatible = "regulator-fixed";
regulator-name = "dphy3_vcc12v_buck4";
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
gpio = <&i2c7_nca9539_gpio 14 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
off-on-delay-us = <16000>;
vin-supply = <&vcc12v_dcin>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
};
&dfi {
status = "disabled";
};
&dmc {
status = "disabled";
};
&gmac1 {
status = "disabled";
};
&hym8563 {
status = "disabled";
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m0_xfer>;
};
/*edp*/
&i2c3_max96752 {
use-reg-check-work;
vpower-supply = <&lcd1_vcc12v_buck>;
};
/*edp touch*/
&i2c3_himax {
himax,irq-gpio = <&gpio0 RK_PB6 IRQ_TYPE_EDGE_FALLING>;
};
/*dp*/
&i2c5_max96745 {
lock-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
};
&i2c5_ilitek {
interrupt-parent = <&gpio4>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
};
/*dp*/
&i2c5_max96752 {
use-reg-check-work;
vpower-supply = <&lcd2_vcc12v_buck>;
};
&i2c8_max96789 {
route-enable;
};
/*dsi*/
&i2c8_max96752 {
use-reg-check-work;
vpower-supply = <&lcd3_vcc12v_buck>;
};
&dp2lvds_backlight0 {
pwms = <&pwm2_8ch_7 0 25000 0>;
};
&edp2lvds_backlight0 {
pwms = <&pwm0_2ch_0 0 25000 0>;
};
/* edp->serdes->lvds_panel */
&pwm0_2ch_0 {
pinctrl-0 = <&pwm0m3_ch0>;
};
/* dp->serdes->lvds_panel */
&pwm2_8ch_7 {
pinctrl-0 = <&pwm2m3_ch7>;
};
&pinctrl {
touch {
//dsi-i2c8
touch_gpio_dsi: touch-gpio-dsi {
rockchip,pins =
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
//dp-i2c5
touch_gpio_dp: touch-gpio-dp {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
//edp0-i2c3
touch_gpio_edp: touch-gpio-edp {
rockchip,pins =
<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
vcc5v0-buck {
vcc5v0_buck_en: vcc5v0-buck-en {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
cluster-buck {
cluster_buck_en: cluster-buck-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&rkvpss {
status = "okay";
};
&rkvpss_mmu {
status = "okay";
};
&rkvpss_vir0 {
status = "okay";
};
&route_dsi {
status = "okay";
};
&sdmmc {
status = "disabled";
};
&ufs {
status = "disabled";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
//vbus-supply = <&usb_otg_vcc5v_buck>;
status = "okay";
};
&u2phy1_otg {
phy-supply = <&usb_host_vcc5v_buck>;
status = "okay";
};
&usbdp_phy {
maximum-speed = "high-speed";
status = "okay";
};
&usb_drd1_dwc3 {
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
status = "okay";
};

5
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb.dtsi
View File

@@ -238,6 +238,11 @@
status = "okay";
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd_n>;
};
&i2c0 {
s35390a: s35390a@30 {
compatible = "sii,s35390a";

35
arch/arm64/boot/dts/rockchip/rk3576-vehicle.dtsi
View File

@@ -251,6 +251,25 @@
goodix,rst-gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_LOW>;
};
hynitron: hynitron@5a {
status = "disabled";
compatible = "hyn,3240";
reg = <0x5a>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c2 {
@@ -305,6 +324,22 @@
<0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {

22
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@@ -2487,6 +2487,28 @@
status = "disabled";
};
cci: cci@27500000 {
compatible = "arm,cci-500";
reg = <0x0 0x27500000 0x0 0x100000>;
ranges = <0x0 0x0 0x27500000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
pmu@10000 {
compatible = "arm,cci-500-pmu,r0";
reg = <0x10000 0x80000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
};
};
rknpu: npu@27700000 {
compatible = "rockchip,rk3576-rknpu";
reg = <0x0 0x27700000 0x0 0x8000>,

35
arch/arm64/boot/dts/rockchip/rk3576s-evb.dtsi
View File

@@ -611,6 +611,25 @@
goodix,rst-gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PC5 IRQ_TYPE_LEVEL_LOW>;
};
hynitron: hynitron@5a {
status = "disabled";
compatible = "hyn,3240";
reg = <0x5a>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c2 {
@@ -667,6 +686,22 @@
<0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {

5
arch/arm64/boot/dts/rockchip/rk3576s-evb1.dtsi
View File

@@ -247,6 +247,11 @@
status = "okay";
};
&hynitron {
status = "okay";
power-supply = <&vcc3v3_lcd_n>;
};
&i2c2 {
status = "okay";

7
arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
View File

@@ -280,6 +280,11 @@
mem-supply = <&vdd_cpu_big1_mem_s0>;
};
&display_subsystem {
clocks = <&hdptxphy_hdmi0>, <&hdptxphy_hdmi1>;
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
};
&dsi0 {
status = "disabled";
//rockchip,lane-rate = <1000>;
@@ -291,6 +296,7 @@
reset-delay-ms = <10>;
enable-delay-ms = <10>;
prepare-delay-ms = <10>;
init-delay-ms = <10>;
unprepare-delay-ms = <10>;
disable-delay-ms = <60>;
width-mm = <68>;
@@ -625,6 +631,7 @@
reset-delay-ms = <10>;
enable-delay-ms = <10>;
prepare-delay-ms = <10>;
init-delay-ms = <10>;
unprepare-delay-ms = <10>;
disable-delay-ms = <10>;
width-mm = <68>;

4
arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts
View File

@@ -83,6 +83,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c6 {
status = "disabled";
};

35
arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi
View File

@@ -496,6 +496,25 @@
goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c7 {
@@ -634,6 +653,22 @@
<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

35
arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi
View File

@@ -503,6 +503,25 @@
goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c5m3_xfer {
@@ -795,6 +814,22 @@
<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

4
arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts
View File

@@ -118,6 +118,10 @@
status = "okay";
};
&hynitron {
status = "disabled";
};
&i2c6 {
clock-frequency = <400000>;
status = "okay";

35
arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi
View File

@@ -328,6 +328,25 @@
goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c7 {
@@ -436,6 +455,22 @@
<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

4
arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts
View File

@@ -87,6 +87,10 @@
status = "okay";
};
&hynitron {
status = "disabled";
};
&i2c5 {
clock-frequency = <400000>;
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts
View File

@@ -87,6 +87,10 @@
status = "okay";
};
&hynitron {
status = "disabled";
};
&i2c5 {
clock-frequency = <400000>;
status = "okay";

35
arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
View File

@@ -984,6 +984,25 @@
goodix,irq-gpio = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c7 {
@@ -1103,6 +1122,22 @@
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
<4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
ts_int_active: ts_int_active {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

35
arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi
View File

@@ -268,6 +268,25 @@
goodix,irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c8 {
@@ -383,6 +402,22 @@
<0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

35
arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi
View File

@@ -341,6 +341,25 @@
goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2s5_8ch {
@@ -418,6 +437,22 @@
<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

4
arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts
View File

@@ -87,6 +87,10 @@
status = "disabled";
};
&hynitron {
status = "disabled";
};
&i2c6 {
status = "disabled";
};

35
arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi
View File

@@ -549,6 +549,25 @@
goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
power-supply = <&vcc3v3_lcd_n>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c6 {
@@ -707,6 +726,22 @@
<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

34
arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi
View File

@@ -560,6 +560,24 @@
goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
hynitron: hynitron@5a {
compatible = "hyn,3240";
reg = <0x5a>;
pinctrl-names = "ts_active","ts_suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
max-touch-number = <5>;
display-coords = <0 0 1080 1920>;
pos-swap = <0>;
posx-reverse = <0>;
posy-reverse = <0>;
};
};
&i2c6 {
@@ -774,6 +792,22 @@
<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_active: ts_int_active {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_reset_active: ts_reset_active {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
};
ts_int_suspend: ts_int_suspend {
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
};
ts_reset_suspend: ts_reset_suspend {
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb {

Some files were not shown because too many files have changed in this diff Show More