512465e0c0
Signed-off-by: Liang Chen <cl@rock-chips.com> Change-Id: I81430bfcce410ddf9205e1b37482b7b869e4f556
46 lines
832 B
Plaintext
46 lines
832 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*/
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#include "rk356x.dtsi"
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/ {
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compatible = "rockchip,rk3566pro", "rockchip,rk3566";
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};
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&pipegrf {
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compatible = "rockchip,rk3566-pipe-grf", "syscon";
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};
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&power {
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power-domain@RK3568_PD_PIPE {
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reg = <RK3568_PD_PIPE>;
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clocks = <&cru PCLK_PIPE>;
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pm_qos = <&qos_pcie2x1>,
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<&qos_sata1>,
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<&qos_sata2>,
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<&qos_usb3_0>,
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<&qos_usb3_1>;
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#power-domain-cells = <0>;
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};
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};
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&rkisp {
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rockchip,iq-feature = /bits/ 64 <0x1BFBF7FE67FF>;
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};
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&usbdrd_dwc3 {
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phys = <&u2phy0_otg>;
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phy-names = "usb2-phy";
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extcon = <&usb2phy0>;
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maximum-speed = "high-speed";
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snps,dis_u2_susphy_quirk;
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snps,usb2-lpm-disable;
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};
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/delete-node/ &route_edp;
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/delete-node/ &vp0_out_edp;
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/delete-node/ &vp1_out_edp;
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/delete-node/ &edp;
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