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clk/rockchip/regmap: rk618: Bypass PLL by default

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Fixes: 962d002400 ("clk/rockchip/regmap: Prepare RK628 PLL support")
Change-Id: I9d76d96f0aa73e97f8ab9ce47f5ac28f22608342
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2021-10-20 11:44:29 +08:00
committed by Tao Huang
parent 8965ce1d73
commit 2d50781c01
1 changed files with 3 additions and 0 deletions
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3
drivers/clk/rockchip/regmap/clk-rk618.c
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@@ -370,6 +370,9 @@ static int rk618_cru_probe(struct platform_device *pdev)
strlcpy(lcdc1_dclkp_name, parent_name,
sizeof(lcdc1_dclkp_name));
regmap_write(cru->regmap, RK618_CRU_PLL0_CON0, 0x80008000);
regmap_write(cru->regmap, RK618_CRU_PLL1_CON0, 0x80008000);
rk618_clk_register_plls(cru);
rk618_clk_register_muxes(cru);
rk618_clk_register_dividers(cru);