From 2d50781c0198d085ffc32e7339f385836ec5efa2 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 20 Oct 2021 11:44:29 +0800 Subject: [PATCH] clk/rockchip/regmap: rk618: Bypass PLL by default Fixes: 962d0024000d ("clk/rockchip/regmap: Prepare RK628 PLL support") Change-Id: I9d76d96f0aa73e97f8ab9ce47f5ac28f22608342 Signed-off-by: Wyon Bi --- drivers/clk/rockchip/regmap/clk-rk618.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/rockchip/regmap/clk-rk618.c b/drivers/clk/rockchip/regmap/clk-rk618.c index c780f502b354..45cfc1aae886 100644 --- a/drivers/clk/rockchip/regmap/clk-rk618.c +++ b/drivers/clk/rockchip/regmap/clk-rk618.c @@ -370,6 +370,9 @@ static int rk618_cru_probe(struct platform_device *pdev) strlcpy(lcdc1_dclkp_name, parent_name, sizeof(lcdc1_dclkp_name)); + regmap_write(cru->regmap, RK618_CRU_PLL0_CON0, 0x80008000); + regmap_write(cru->regmap, RK618_CRU_PLL1_CON0, 0x80008000); + rk618_clk_register_plls(cru); rk618_clk_register_muxes(cru); rk618_clk_register_dividers(cru);