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arm64: dts: rockchip: rk3588-evb: Set pcie30x4_clkreqn_m1 gpio output low

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The new hardware design will connect clkreq to the control pin of the
external clock, so the default output should be low level。

Change-Id: I2c99b90b7de359c8f32576d5f6eb7157c7a4a7b5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2023-06-30 11:29:42 +08:00
committed by Tao Huang
parent 8012da0685
commit 0a17a29a19
6 changed files with 51 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi
View File

@@ -558,6 +558,8 @@
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
status = "okay";
};
@@ -610,6 +612,12 @@
};
};
pcie30x4 {
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
rtl8111 {
rtl8111_isolate: rtl8111-isolate {
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;

8
arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi
View File

@@ -385,6 +385,8 @@
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
status = "okay";
};
@@ -414,6 +416,12 @@
};
};
pcie30x4 {
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;

8
arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
View File

@@ -1044,6 +1044,8 @@
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
status = "okay";
};
@@ -1073,6 +1075,12 @@
};
};
pcie30x4 {
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
rtl8111 {
rtl8111_isolate: rtl8111-isolate {
rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;

10
arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi
View File

@@ -230,9 +230,19 @@
num-lanes = <2>;
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
status = "okay";
};
&pinctrl {
pcie30x4 {
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm9 {
pinctrl-0 = <&pwm9m2_pins>;
status = "okay";

8
arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi
View File

@@ -627,6 +627,8 @@
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
status = "okay";
};
@@ -679,6 +681,12 @@
};
};
pcie30x4 {
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;

9
arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi
View File

@@ -426,6 +426,8 @@
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie30x4_clkreqn_m1>;
status = "okay";
};
@@ -694,6 +696,13 @@
};
};
pcie30x4 {
pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
rtc {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;