From 0a17a29a197a6d24eb2601d1e8bcf513799aadc0 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 30 Jun 2023 11:29:42 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588-evb: Set pcie30x4_clkreqn_m1 gpio output low MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new hardware design will connect clkreq to the control pin of the external clock, so the default output should be low level。 Change-Id: I2c99b90b7de359c8f32576d5f6eb7157c7a4a7b5 Signed-off-by: Jon Lin --- arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi | 9 +++++++++ 6 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi index 431a5bbdb641..a10dad37f9cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi @@ -558,6 +558,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -610,6 +612,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + rtl8111 { rtl8111_isolate: rtl8111-isolate { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi index 03c9c36d0656..809c48754bf2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi @@ -385,6 +385,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -414,6 +416,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi index 4213e54ab0b7..eca37c90b301 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi @@ -1044,6 +1044,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -1073,6 +1075,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + rtl8111 { rtl8111_isolate: rtl8111-isolate { rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi index 8e783a98735c..07aaf22b1361 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi @@ -230,9 +230,19 @@ num-lanes = <2>; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; +&pinctrl { + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + &pwm9 { pinctrl-0 = <&pwm9m2_pins>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi index 742d57254f3e..9e41ea8cfabf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi @@ -627,6 +627,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -679,6 +681,12 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi index 5c345b2cde2d..925a81e45cd3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi @@ -426,6 +426,8 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; status = "okay"; }; @@ -694,6 +696,13 @@ }; }; + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtc { rtc_int: rtc-int { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;