multiple-os: don't disable timer6

It seems kernel will use it

Change-Id: Idcd61cdf4f3ee8e038883fc0e8699b422fd48ff5
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arch/arm/boot/dts/rk3288-miniarm.dts

@@ -424,10 +424,6 @@
 	status = "okay";
 };
 
-&uart1 {
-	status = "okay";
-};
-
 &uart2 {
 	status = "okay";
 };

arch/arm/boot/dts/rk3288.dtsi

@@ -81,7 +81,11 @@
 			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+#if 0
 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+#else
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>;
+#endif
 	};
 
 	cpus {
@@ -113,6 +117,7 @@
 			resets = <&cru SRST_CORE2>;
 			operating-points-v2 = <&cpu0_opp_table>;
 		};
+#if 0
 		cpu3: cpu@503 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
@@ -120,6 +125,7 @@
 			resets = <&cru SRST_CORE3>;
 			operating-points-v2 = <&cpu0_opp_table>;
 		};
+#endif
 	};
 
 	cpu0_opp_table: opp_table0 {
@@ -260,6 +266,10 @@
 		dma-unusable@fe000000 {
 			reg = <0xfe000000 0x1000000>;
 		};
+
+        uboot@50000000 {
+			reg = <0x50000000 0x10000000>;
+		};
 	};
 
 	xin24m: oscillator {
@@ -1530,6 +1540,12 @@
 		interrupts = <GIC_PPI 9 0xf04>;
 	};
 
+    uboot {
+		compatible = "rockchip,uboot";
+		clocks = <&cru PCLK_TIMER>, <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+		clock-names = "pclk_timer","uart1_sclk", "uart1_pclk";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3288-pinctrl";
 		rockchip,grf = <&grf>;

arch/arm/mach-rockchip/Makefile

@@ -1,7 +1,7 @@
 CFLAGS_platsmp.o := -march=armv7-a
 
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
-obj-$(CONFIG_PM_SLEEP) += pm.o rk3288_ddr_suspend.o
+obj-$(CONFIG_PM_SLEEP) += pm.o rk3288_ddr_suspend.o uboot.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 
 obj-y += embedded/

arch/arm/mach-rockchip/platsmp.c

@@ -76,6 +76,9 @@ static int pmu_set_power_domain(int pd, bool on)
 	struct reset_control *rstc = rockchip_get_core_reset(pd);
 	int ret;
 
+	if (pd == 3)
+		return 0;
+
 	if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
 		pr_err("%s: could not get reset control for core %d\n",
 		       __func__, pd);
@@ -126,6 +129,8 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	int ret;
 
+	BUG_ON(cpu == 3);
+
 	if (!sram_base_addr || (has_pmu && !pmu)) {
 		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
 		return -ENXIO;

arch/arm/mach-rockchip/rockchip.c

@@ -45,16 +45,16 @@ static void __init rockchip_timer_init(void)
 		 * So make sure it is running during early boot.
 		 */
 		reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
-		if (reg_base) {
+		// if (reg_base) {
-			writel(0, reg_base + 0x30);
+		// 	writel(0, reg_base + 0x30);
-			writel(0xffffffff, reg_base + 0x20);
+		// 	writel(0xffffffff, reg_base + 0x20);
-			writel(0xffffffff, reg_base + 0x24);
+		// 	writel(0xffffffff, reg_base + 0x24);
-			writel(1, reg_base + 0x30);
+		// 	writel(1, reg_base + 0x30);
-			dsb();
+		// 	dsb();
-			iounmap(reg_base);
+		// 	iounmap(reg_base);
-		} else {
+		// } else {
-			pr_err("rockchip: could not map timer7 registers\n");
+		// 	pr_err("rockchip: could not map timer7 registers\n");
-		}
+		// }
 
 		/*
 		 * Disable auto jtag/sdmmc switching that causes issues

arch/arm/mach-rockchip/uboot.c

@@ -0,0 +1,87 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iommu.h>
+#include <linux/jiffies.h>
+#include <linux/list.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+
+static int uboot_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct clk *reserved_clk;
+	int i = 0;
+
+	/* reserve clock */
+	while(1) {
+		
+		reserved_clk = of_clk_get(np, i++);
+		if (IS_ERR(reserved_clk))
+			break;
+
+		if (clk_prepare_enable(reserved_clk)) {
+			pr_err("Failed to enable clock for uboot\n");
+			break;
+		}
+	}
+
+	/* setup irq */
+
+	return 0;
+}
+
+static int uboot_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id uboot_dt_ids[] = {
+	{ .compatible = "rockchip,uboot" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rk_iommu_dt_ids);
+
+static struct platform_driver uboot_driver = {
+	.probe = uboot_probe,
+	.remove = uboot_remove,
+	.driver = {
+		   .name = "uboot",
+		   .of_match_table = uboot_dt_ids,
+	},
+};
+
+static int __init uboot_init(void)
+{
+	return platform_driver_register(&uboot_driver);
+}
+static void __exit uboot_exit(void)
+{
+	platform_driver_unregister(&uboot_driver);
+}
+
+subsys_initcall(uboot_init);
+module_exit(uboot_exit);
+
+MODULE_DESCRIPTION("Uboot Helper for Rockchip");
+MODULE_AUTHOR("Jacob Chen <jacob2.chen@rock-chips.com>");
+MODULE_ALIAS("platform:rockchip-uboot");
+MODULE_LICENSE("GPL v2");

drivers/pinctrl/pinctrl-rockchip.c

@@ -1752,7 +1752,6 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
 	if (ret < 0)
 		return ret;
 
-	clk_enable(bank->clk);
 	spin_lock_irqsave(&bank->slock, flags);
 
 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
@@ -1764,7 +1763,6 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 
 	spin_unlock_irqrestore(&bank->slock, flags);
-	clk_disable(bank->clk);
 
 	return 0;
 }
@@ -2193,7 +2191,6 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 	unsigned long flags;
 	u32 data;
 
-	clk_enable(bank->clk);
 	spin_lock_irqsave(&bank->slock, flags);
 
 	data = readl(reg);
@@ -2203,7 +2200,6 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 	writel(data, reg);
 
 	spin_unlock_irqrestore(&bank->slock, flags);
-	clk_disable(bank->clk);
 }
 
 /*
@@ -2215,9 +2211,7 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
 	struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 	u32 data;
 
-	clk_enable(bank->clk);
 	data = readl(bank->reg_base + GPIO_EXT_PORT);
-	clk_disable(bank->clk);
 	data >>= offset;
 	data &= 1;
 	return data;
@@ -2354,7 +2348,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
 	if (ret < 0)
 		return ret;
 
-	clk_enable(bank->clk);
 	spin_lock_irqsave(&bank->slock, flags);
 
 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
@@ -2412,7 +2405,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
 	default:
 		irq_gc_unlock(gc);
 		spin_unlock_irqrestore(&bank->slock, flags);
-		clk_disable(bank->clk);
 		return -EINVAL;
 	}
 
@@ -2421,7 +2413,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
 
 	irq_gc_unlock(gc);
 	spin_unlock_irqrestore(&bank->slock, flags);
-	clk_disable(bank->clk);
 
 	return 0;
 }
@@ -2431,10 +2422,8 @@ static void rockchip_irq_suspend(struct irq_data *d)
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 	struct rockchip_pin_bank *bank = gc->private;
 
-	clk_enable(bank->clk);
 	bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
 	irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
-	clk_disable(bank->clk);
 }
 
 static void rockchip_irq_resume(struct irq_data *d)
@@ -2442,27 +2431,7 @@ static void rockchip_irq_resume(struct irq_data *d)
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 	struct rockchip_pin_bank *bank = gc->private;
 
-	clk_enable(bank->clk);
 	irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
-	clk_disable(bank->clk);
-}
-
-static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
-{
-	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	struct rockchip_pin_bank *bank = gc->private;
-
-	clk_enable(bank->clk);
-	irq_gc_mask_clr_bit(d);
-}
-
-void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
-{
-	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	struct rockchip_pin_bank *bank = gc->private;
-
-	irq_gc_mask_set_bit(d);
-	clk_disable(bank->clk);
 }
 
 static int rockchip_interrupts_register(struct platform_device *pdev,
@@ -2473,7 +2442,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 	struct irq_chip_generic *gc;
 	int ret;
-	int i, j;
+	int i;
 
 	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
 		if (!bank->valid) {
@@ -2482,19 +2451,11 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
 			continue;
 		}
 
-		ret = clk_enable(bank->clk);
-		if (ret) {
-			dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
-				bank->name);
-			continue;
-		}
-
 		bank->domain = irq_domain_add_linear(bank->of_node, 32,
 						&irq_generic_chip_ops, NULL);
 		if (!bank->domain) {
 			dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
 				 bank->name);
-			clk_disable(bank->clk);
 			continue;
 		}
 
@@ -2505,7 +2466,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
 			dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
 				bank->name);
 			irq_domain_remove(bank->domain);
-			clk_disable(bank->clk);
 			continue;
 		}
 
@@ -2523,9 +2483,8 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
 		gc->chip_types[0].regs.mask = GPIO_INTMASK;
 		gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
 		gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
-		gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
+		gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
-		gc->chip_types[0].chip.irq_unmask =
+		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
-						  rockchip_irq_gc_mask_clr_bit;
 		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
 		gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
 		gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
@@ -2534,12 +2493,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
 
 		irq_set_chained_handler_and_data(bank->irq,
 						 rockchip_irq_demux, bank);
-
-		/* map the gpio irqs here, when the clock is still running */
-		for (j = 0 ; j < 32 ; j++)
-			irq_create_mapping(bank->domain, j);
-
-		clk_disable(bank->clk);
 	}
 
 	return 0;
@@ -2657,7 +2610,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
 	if (IS_ERR(bank->clk))
 		return PTR_ERR(bank->clk);
 
-	return clk_prepare(bank->clk);
+	return clk_prepare_enable(bank->clk);
 }
 
 static const struct of_device_id rockchip_pinctrl_dt_match[];