Since the PSR feature can help to reduce the power consumption, the
Source device, which can support PSR function, should enable PSR if
the PSR capability of Sink device is detected rather than depending
on the user to add 'support-psr' DTS property manually.
Change-Id: I2f51312621f62519f388e06561fb61f01145256b
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Before this commit, the drm_self_refresh_helper_init() was called
in &component_ops.bind() of VOP/VOP2 drivers. The VOP or VPs,
which do not want to enable PSR functionality, will also initialize
the self refresh helper.
Since it wastes resources(e.g., allocating &drm_self_refresh_data and
initializing &drm_self_refresh_data.entry_work), we move the init and
cleanup process from bind()/unbind() of VOP/VOP2 drivers to the ones
of eDP/RGB drivers, which can support PSR functionality.
Change-Id: Ie7643b54f42ea3d5ab7b0cdbc77ccfdb06c614b9
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
If no errno assignment for this case, there will be a warning:
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:5754 vop_create_crtc() warn:
missing error code 'ret'
Change-Id: I9e78fe99b3ca24d8734ee286b1dc1f0908721f25
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
First of all, since the PSR feature can help to reduce the power
consumption, the Source device, which can support PSR function,
should enable PSR if the PSR capability of Sink device is detected
rather than depending on the user to add 'support-psr' DTS property
manually.
Different platforms that use the same Analogix DP bridge driver may
have different methods for parsing the PSR capability. Therefore, add
a new flag &analogix_dp_plat_data.disable_psr to disable PSR forcely,
which set in the platform side, should be more reasonable.
If the user truly does not want to enable PSR function or the Panel
has something wrong with it, the property 'rockchip,disable-psr' will
be helpful.
Fixes: 9622f2d0f1 ("drm/bridge: analogix_dp: disable PSR feature by default")
Change-Id: Id2fce34857df80de5a1ec97f342709a6e2840ed4
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
drivers/pci/controller/dwc/pcie-dw-dmatest.c:157:5: error: no previous prototype for 'rk_pcie_local_dma_tobus_block' [-Werror=missing-prototypes]
Change-Id: I616a4759d856a72b469996a3c6f07e4af90d5616
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Since the PSR feature can help to reduce the power consumption, the
Source device, which can support PSR function, should enable PSR if
the PSR capability of Sink device is detected.
If the user truly does not want to enable PSR function or the Panel
has something wrong with it, the property 'rockchip,disable-psr' will
be helpful.
Change-Id: I03b3c83c7c88ea3fc3ccd447e5c5da49e16f22a9
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
After converting analogix_dp.txt to yaml, the descriptions of
properties for dual-channel and split modes, which have been
already supported, should be added synchronously.
Change-Id: I8a66ef3ed8c469eca0c9d6e06a827c1f1a8d58a1
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RK3568 eDP TX controller is almost the same as that of RK3399.
It supports RBR/HBR with 1/2/4 lanes and the max supported resolution
is 2560x1600p60.
The slight difference with RK3399 is the newly added 'apb' reset,
which is just like that of RK3588/RK3576.
Change-Id: Ifd5bc2d8f337b794a6d2983b689d2bd2271d78c2
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RK3576 eDP TX controller is the same as that of RK3588.
Change-Id: I3f32329866bc70f6f26132eb583f520e39f53594
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Compared with RK3288/RK3399, the HBR2 link rate support is the main
improvement of RK3588 eDP TX controller, and there are also two
independent eDP display interfaces on RK3588 Soc.
The newly added 'apb' reset is to ensure the APB bus of eDP controller
works well on the RK3588 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Change-Id: If3864613762898624ba39ad0395516a4ebb02732
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250310104114.2608063-10-damon.ding@rock-chips.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
(cherry picked from commit f855146263b14abadd8d5bd0e280e54fbab3bd18)
If the DSC mode with a compression rate lower than 0.375 is to
be supported, the dclk clock source of the VOP bound to HDMI must
be a CRU PLL that supports fractional frequency division.
However, in most scenarios, HDMI is unable to be assigned such a
PLL. So in this scenario, instead of enabling DSC, we switch to
YUV420 format.
Change-Id: I450cdd5857e4384894651ed063fac152a8d9bb0f
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Only searches rockchip,pvtpll-table when bin-specific property is absent.
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: Ic728e39851cdd8c32970d81249cf295a3b8d6aeb
Avoid auto_gating/int_mask register state loss after reset
Change-Id: Ie341f0f58f398476daacffdd90565d39c68faa54
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
1. Resetting only core_clk will cause abnormal src1 status in blend
scenarios, so both aclk and core_clk must be reset.
2. Avoid the issue by shielding the wrong interrupt.
Fixes: a2a7ce0bf0 ("video: rockchip: rga3: add fix for hardware issuewith RK3576")
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I3cb0034f6c3090faca19cea2c2f5b375388271f8
Reset pmic and output NPOR signal 5ms when system reboot.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8c59ed22342617cf555e54c3fb43821203aae70c
The following trace can be seen if usb is connecting to
Host while do rockchip_chg_detect_work.
DEBUG_LOCKS_WARN_ON(rt_mutex_owner(lock) != current)
WARNING: CPU: 6 PID: 512 at kernel/locking/rtmutex-debug.c:47 debug_rt_mutex_unlock+0x58/0x64
Modules linked in:
CPU: 6 PID: 512 Comm: kworker/6:3 Not tainted 5.10.226-rt89 #186
Hardware name: Rockchip RK3588 EVB1 LP4 V10 Board (DT)
Workqueue: events rockchip_chg_detect_work
pstate: 60c00089 (nZCv daIf +PAN +UAO -TCO BTYPE=--)
pc : debug_rt_mutex_unlock+0x58/0x64
lr : debug_rt_mutex_unlock+0x58/0x64
......
Call trace:
debug_rt_mutex_unlock+0x58/0x64
__rt_mutex_unlock+0x48/0xf8
_mutex_unlock+0xc/0x14
rockchip_chg_detect_work+0x44c/0x6f0
process_one_work+0x1bc/0x27c
worker_thread+0x268/0x488
kthread+0x170/0x210
ret_from_fork+0x10/0x18
This issue can cause the preempt-rt Linux kernel to crash.
The reason is that all mutexes in preempt-rt have been replaced
with rt_mutexes. An rt_mutex has a PI (Priority Inversion) feature,
which means that when a high-priority task waits for a lock held
by a low-priority task, the priority of the low-priority task is
elevated. A linked list is established on p->pi_waiters. This
requires that lock/unlock operations be handled by the same task.
If unlock is performed and pi_waiters is released by another task,
the task that holds the lock will encounter an exception when
accessing pi_waiters. When executing rockchip_chg_detect_work,
a schedule_delayed_work operation is performed while holding the
mutex lock, causing the mutex lock to be released by a different
worker task, which triggers a kernel panic.
This patch use kthread_work instead of delayed_work to avoid
long-running chg work affecting other tasks in the system workqueue.
And also avoid chg work to be scheduled while hold a mutex lock.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I1e49a22f002b0dfcf0e04d243d99624d34c9a701
Panel TPM270WR1 supports 3840x2160p144 with 8lanes and local dimming
through SPI interface.
Change-Id: I0b7e33503d76661510bb99364b041ea18e2d4513
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The dimming panel driver supports to adjust the backlight brightness
of different zones.
Change-Id: Ieafa865fb9ad5bc184fb148c4a36fb3cbd4e854c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
When PD_VPU power domain is off, the pin state of ebc is X state.
Set the EBC pin control to GPIO and pull low to ensure that it remains
in low state.
Change-Id: Iafa70622f8fce475c307edfb6d4d4ad9635a43cd
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
As the Table 4-24 in eDP 1.4 spec, the Sink device can only support
Main-Link rate selection via SUPPORTED_LINK_RATES when the value of
DPCD MAX_LINK_RATE is 00h. If MAX_LINK_RATE and SUPPORTED_LINK_RATES
are both non-zero, the Sink device can support both methods.
In practice, if MAX_LINK_RATE is not 00h and SUPPORTED_LINK_RATES
contains non-zero values, sometimes the sink device can only support
to set link rate via LINK_BW_SET. In such case, there will be errors
if set the link rate read from SUPPORTED_LINK_RATES to LINK_RATE_SET.
The panel vendor may explain this is to ensure the same Sink firmware
remains compatible across different versions of the eDP spec. Or the
Main-Link rate selection method has not been fully verified.
In order to avoid these unexpected cases, MAX_LINK_RATE/LINK_BW_SET
method will be selected first if MAX_LINK_RATE is non-zero for eDP
panels that support v1.4 or higher.
Previous patch for link rate table parsing:
commit 31702584f8 ("drm/bridge: analogix_dp: add support to parse link rate for eDP v1.4")
Change-Id: Ic8aedcec2c60584fedddc575b2a91c2eba7c8219
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
set " bt_port = "/dev/ttyS*" " under wireless_bluetooth
Change-Id: I20298c3679d4d66f604e413198f1c7f6c89be46b
Signed-off-by: lin longjian <llj@rock-chips.com>
According to SI test report, BT1120/BT656 drive strength should be
set.
Change-Id: I59aa29fc1c24b0b152fd96a260197fab21790d75
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
According to SI test report, BT1120/BT656 delay line should be set.
Change-Id: Id30655e15daac20ed126683768bab90d7425cb83
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
