SPI Nand support these flowing ECC status:
1.ECC OK.
2.ECC bits flip is correctable and not reach it's ecc_strength.
3.ECC bits flip is correctable and reach it's ecc_strength.
4.ECC failed.
Case2/3 rely on ecc_strength value, or will be set as ECC ok although
it's accept.
Change-Id: Ia39b0b17ca8f1b3a94b43a49a607a37d35fd185f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Because I2STX_CKE has been set to disable in rk817_codec_shutdown,
then I2STX_CKE_EN should be set when recording.
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Change-Id: If1201ad12e33dca21eb443bd32750a73c1fa9f67
During the playback, if PLL_PW_DOWN and PLL_PW_UP is performed,
a POP sound is generated.
When the sample rate does not change, do not restart the pll.
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Change-Id: I83de976e6e2752a85c57fbc4d4eb6bd5f1b21fbf
When switching sample rates, the clock settings are as follows:
- For 48K, MCLK = 256fs = 256 * 48K = 12288K
- For 16K, MCLK = 256fs = 256 * 16K = 4096K
- For 8K, MCLK = 256fs = 256 * 8K = 2048K
The `set_sysclk` function in the soc i2s_tdm controller does not
actually perform `clk_set_rate`; it merely passes the parameters.
The actual `clk_set_rate` is called during `i2s_tdm_hw_params`.
However, `rk817_hw_params` performs `restart_clk_apll` inside,
which sets the PLL parameters that do not match the MCLK,
resulting in silence. To resolve this, clk_set_rate for the MCLK
frequency should be called within the set_sysclk function.
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I3ad233542a5e8b16ae72f829e086a25f5be4a095
The I2S part of RK817 work as slave mode require BCLK on
first, otherwise, there will make the L/R invert.
On the stage hw_params, the BCLK maybe off. so, let's move
it into mute stage to fix this.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I3b9a7030342281a596e16c025f42c49a79c3a5df
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
When IRQ BALANCING is enable, the log below is show:
fiq_debugger:cpu 0 not responding,reverting to cpu 6
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ic5a1786ecb72dc4b28e9b9fa8428065e111e55ee
Workaround for FIFO clear on SLAVE mode:
A Suggest to do reset hclk domain and then do mclk
domain, especially for SLAVE mode without CLK in.
at last, recovery regmap config.
B Suggest to switch to MASTER, and then do FIFO clr,
at last, bring back to SLAVE.
Now we choose plan B here.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I1884659df7fa9052477652b7b0315da21e3165c2
If the hid transfer with size divisible to EP0 max packet
size, it needs to set the req->zero to true, then the usb
controller can transfer a zero length packet at the end
according to the USB 2.0 spec.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iae8c06966efe49c3a33213f9c36dd752633e8bd1
This adds the necessary data for handling eFuse on the rk3036.
Change-Id: Ifef7bcdb8ddb1dc04546e4d7dad0c0a24ab974f3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
In RK3288/RK3399, there is a problem with the definition of the
`fmt_10` field in the VOP WIN register. The original `fmt_10`
definition conflicts with the `lb_mode` definition.
This will cause the `lb_mode` function to be affected, there may be
problems with incorrect colors displayed, incorrect window sizes,
image flickering, etc.
This patch correct `fmt_10` field to the expected value in TRM.
Change-Id: I0f9f23c459dc5870532e28b74053a9b4dc606de0
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The driver is using ciu-drive instead of ciu-drv.
They were converted by:
sed -i "s/ciu-drv/ciu-drive/g" `grep ciu-drv -rl arch/arm64/boot/dts/rockchip/*`
Change-Id: I7e5be98a46d7eb5d29b5b0fe0280ea8b91c60406
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
If mcu_hold_mode is 1, set 1 to mcu_frame_st will
refresh one frame from ddr. So mcu_frame_st is needed
to be initialized as 0.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I75d755826dbbdd229da3c3db15d4682dc2bd13a0
This patch re-enable port polling if ehci maintained
power in suspend as well as ehci lost power in suspend.
Change-Id: If970d33323582a8c4bd4158a4b4fcc3f08366ceb
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch two issues for ehci host hs reset work.
1. If the port owner has been set to ohci, the port
status reg of ehci is invalid, in this case, it
needs to schedule ehci hs reset work if ohci root
hub has no configured child.
2. Avoid triggering hs reset work for normal linestate
in hotplug quickly test.
Change-Id: I4d5f70f83332abc42e8a8b2c875f9da9f76e55d0
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fix two issues for dwc2 host hs reset work.
1. Avoid triggering hs reset work for normal linestate
in hotplug quickly test.
2. If the usb linestate is in abnormal status, the dwc2
controller may stay in low speed, it needs to clear
the HPRT0_PWR to recovery the dwc2 controller before
do high speed handshake.
Change-Id: I7789afb209957646a9537fd775a0ed43dd400aa5
Signed-off-by: William Wu <william.wu@rock-chips.com>
For a more stable system, delete the 528MHz frequency and open
the 666MHz frequency ODT.
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0354c6dde8f39a9b41878446475ee3acbe1be729
Program/Erase/Read Speed
– Page Program time : 450us typical
– BLOCK ERASE time : 4ms typical
– PAGE READ time : 120us maximum (without ECC)
Change-Id: I0c5bc9827788938df028e525e331c0db8d041676
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
SMIC TudorAG and previous versions:
During playback, a POP sound occurs when the recording is opened.
This patch is intended to fix this issue.
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Change-Id: I86f79cd531738113092723e1ef198b093ae472b9
Some PC USB Hosts (e.g Dell laptop) fail to send
SetInterface(AltSet=0) to stop capture/playback
when PC enter suspend or play YouTube Video.
To be compatible with these PC, add this patch to
stop capture/playback prior to start again if the
stream_state is true.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iced57de39b6b88a7c987897dcb123cf8d7cf6473
