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arm64: dts: rockchip: rk3566-evb1-ddr4-v10: links ov02k10 with vicap by mipi split mode

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Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I8547af9aa5d956b2105390bb5cbb962fa9552f7a
This commit is contained in:
Allon Huang
2020-12-23 18:40:02 +08:00
committed by Tao Huang
parent 8378430a70
commit e8fba342ae
1 changed files with 119 additions and 0 deletions
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119
arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi
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@@ -55,6 +55,46 @@
status = "disabled";
};
&csi_dphy {
status = "okay";
/*lane-mode:
* index0: 4 means full mode, 2 means split mode
* index1: 1 means using lane0/1, 2 means using lane2/3
* attention: if lane-mode is not set, default mode is full mode,
* full mode and split mode are mutually exclusive
* eg: rockchip,lane-mode = <2 1>, means using split mode, and using lane0/1
*/
rockchip,lane-mode = <2 2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam1: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov02k10_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&dig_acodec {
status = "disabled";
rockchip,pwm-output-mode;
@@ -147,10 +187,70 @@
<000000000 0x0000 0x0000 0x0000>;
};
&i2c2 {
status = "okay";
ov02k10: ov02k10@36 {
status = "okay";
compatible = "ovti,ov02k10";
reg = <0x36>;
clocks = <&cru CLK_CAM1_OUT>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&cam_clkout1>;
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
ov02k10_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
};
&i2s3_2ch {
status = "disabled";
};
&mipi_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
data-lanes = <1 2>;
};
};
};
};
&mipi_dphy0 {
status = "okay";
};
@@ -182,6 +282,25 @@
status = "disabled";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
data-lanes = <1 2>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&route_dsi0 {
status = "okay";
};