arm64: dts: rockchip: rk3576-evb1-v10: add ipc dual cam dts

Change-Id: Ia6334a78f72dbf648089df230237d3dbc9bb09bd
Signed-off-by: LongChang Ma <chad.ma@rock-chips.com>
This commit is contained in:
LongChang Ma
2024-09-26 20:18:04 +08:00
committed by Tao Huang
parent 795750411d
commit e3a69bab86
3 changed files with 548 additions and 0 deletions

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@@ -246,6 +246,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-edp-NV140QUM-N61.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-hdmi2dp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-image-reverse-demo.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-ipc-4x-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-ipc-dual-cam-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-linux-amp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-lontium-hdmiin.dtb

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@@ -0,0 +1,292 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
* Version Sensor I2C_ADDR Lanes
* v1.0.0 imx415 0x1a lane0~1(dphy1)
* imx415 0x1a lane2~3(dphy2)
*/
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input1: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx415_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_csi2_input>;
};
};
};
};
&csi2_dphy1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input2: endpoint@3 {
reg = <3>;
remote-endpoint = <&imx415_out1>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
&i2c4 {
status = "okay";
pinctrl-0 = <&i2c4m3_xfer>;
imx415_0: imx415@1a {
compatible = "sony,imx415";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M0>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&cam_clk0m0_clk0>;
power-domains = <&power RK3576_PD_VI>;
avdd-supply = <&vcc_mipidcphy0>;
// reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
imx415_out0: endpoint {
remote-endpoint = <&csi_dphy_input1>;
data-lanes = <1 2 3 4>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-0 = <&i2c5m3_xfer>;
imx415_1: imx415@1a {
compatible = "sony,imx415";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMERAOUT_M1>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&cam_clk1m0_clk1>;
power-domains = <&power RK3576_PD_VI>;
avdd-supply = <&vcc_mipicsi0>;
// reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
imx415_out1: endpoint {
remote-endpoint = <&csi_dphy_input2>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output1>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in1>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi1_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir0>;
};
};
};
&rkcif_mipi_lvds1 {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in1: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
port {
mipi1_lvds_sditf: endpoint {
remote-endpoint = <&isp_vir1>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
#address-cells = <1>;
#size-cells = <0>;
isp_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&rkisp_vir1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_lvds_sditf>;
};
};
};
&rkvpss {
status = "okay";
};
&rkvpss_mmu {
status = "okay";
};
&rkvpss_vir0 {
status = "okay";
};
&rkvpss_vir1 {
status = "okay";
};

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@@ -0,0 +1,255 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3576.dtsi"
#include "rk3576-evb1.dtsi"
#include "rk3576-evb1-dual-cam.dtsi"
#include "rk3576-linux.dtsi"
/ {
model = "Rockchip RK3576 EVB1 V10 Board";
compatible = "rockchip,rk3576-evb1-v10", "rockchip,rk3576";
};
&dsi_panel {
status = "okay";
panel-init-sequence = [
39 00 04 ff 98 81 03
15 00 02 01 00
15 00 02 02 00
15 00 02 03 53
15 00 02 04 53
15 00 02 05 13
15 00 02 06 04
15 00 02 07 02
15 00 02 08 02
15 00 02 09 00
15 00 02 0a 00
15 00 02 0b 00
15 00 02 0c 00
15 00 02 0d 00
15 00 02 0e 00
15 00 02 0f 00
15 00 02 10 00
15 00 02 11 00
15 00 02 12 00
15 00 02 13 00
15 00 02 14 00
15 00 02 15 08
15 00 02 16 10
15 00 02 17 00
15 00 02 18 08
15 00 02 19 00
15 00 02 1a 00
15 00 02 1b 00
15 00 02 1c 00
15 00 02 1d 00
15 00 02 1e c0
15 00 02 1f 80
15 00 02 20 02
15 00 02 21 09
15 00 02 22 00
15 00 02 23 00
15 00 02 24 00
15 00 02 25 00
15 00 02 26 00
15 00 02 27 00
15 00 02 28 55
15 00 02 29 03
15 00 02 2a 00
15 00 02 2b 00
15 00 02 2c 00
15 00 02 2d 00
15 00 02 2e 00
15 00 02 2f 00
15 00 02 30 00
15 00 02 31 00
15 00 02 32 00
15 00 02 33 00
15 00 02 34 04
15 00 02 35 05
15 00 02 36 05
15 00 02 37 00
15 00 02 38 3c
15 00 02 39 35
15 00 02 3a 00
15 00 02 3b 40
15 00 02 3c 00
15 00 02 3d 00
15 00 02 3e 00
15 00 02 3f 00
15 00 02 40 00
15 00 02 41 88
15 00 02 42 00
15 00 02 43 00
15 00 02 44 1f
15 00 02 50 01
15 00 02 51 23
15 00 02 52 45
15 00 02 53 67
15 00 02 54 89
15 00 02 55 ab
15 00 02 56 01
15 00 02 57 23
15 00 02 58 45
15 00 02 59 67
15 00 02 5a 89
15 00 02 5b ab
15 00 02 5c cd
15 00 02 5d ef
15 00 02 5e 03
15 00 02 5f 14
15 00 02 60 15
15 00 02 61 0c
15 00 02 62 0d
15 00 02 63 0e
15 00 02 64 0f
15 00 02 65 10
15 00 02 66 11
15 00 02 67 08
15 00 02 68 02
15 00 02 69 0a
15 00 02 6a 02
15 00 02 6b 02
15 00 02 6c 02
15 00 02 6d 02
15 00 02 6e 02
15 00 02 6f 02
15 00 02 70 02
15 00 02 71 02
15 00 02 72 06
15 00 02 73 02
15 00 02 74 02
15 00 02 75 14
15 00 02 76 15
15 00 02 77 0f
15 00 02 78 0e
15 00 02 79 0d
15 00 02 7a 0c
15 00 02 7b 11
15 00 02 7c 10
15 00 02 7d 06
15 00 02 7e 02
15 00 02 7f 0a
15 00 02 80 02
15 00 02 81 02
15 00 02 82 02
15 00 02 83 02
15 00 02 84 02
15 00 02 85 02
15 00 02 86 02
15 00 02 87 02
15 00 02 88 08
15 00 02 89 02
15 00 02 8a 02
39 00 04 ff 98 81 04
15 00 02 00 80
15 00 02 70 00
15 00 02 71 00
15 00 02 66 fe
15 00 02 82 15
15 00 02 84 15
15 00 02 85 15
15 00 02 3a 24
15 00 02 32 ac
15 00 02 8c 80
15 00 02 3c f5
15 00 02 88 33
39 00 04 ff 98 81 01
15 00 02 22 0a
15 00 02 31 00
15 00 02 53 78
15 00 02 50 5b
15 00 02 51 5b
15 00 02 60 20
15 00 02 61 00
15 00 02 62 0d
15 00 02 63 00
15 00 02 a0 00
15 00 02 a1 10
15 00 02 a2 1c
15 00 02 a3 13
15 00 02 a4 15
15 00 02 a5 26
15 00 02 a6 1a
15 00 02 a7 1d
15 00 02 a8 67
15 00 02 a9 1c
15 00 02 aa 29
15 00 02 ab 5b
15 00 02 ac 26
15 00 02 ad 28
15 00 02 ae 5c
15 00 02 af 30
15 00 02 b0 31
15 00 02 b1 2e
15 00 02 b2 32
15 00 02 b3 00
15 00 02 c0 00
15 00 02 c1 10
15 00 02 c2 1c
15 00 02 c3 13
15 00 02 c4 15
15 00 02 c5 26
15 00 02 c6 1a
15 00 02 c7 1d
15 00 02 c8 67
15 00 02 c9 1c
15 00 02 ca 29
15 00 02 cb 5b
15 00 02 cc 26
15 00 02 cd 28
15 00 02 ce 5c
15 00 02 cf 30
15 00 02 d0 31
15 00 02 d1 2e
15 00 02 d2 32
15 00 02 d3 00
39 78 04 ff 98 81 00
05 78 01 11
05 00 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
disp_timings0: display-timings {
native-mode = <&dsi_timing0>;
dsi_timing0: timing0 {
clock-frequency = <66000000>;
hactive = <720>;
vactive = <1280>;
hfront-porch = <40>;
hsync-len = <10>;
hback-porch = <40>;
vfront-porch = <22>;
vsync-len = <4>;
vback-porch = <11>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};