arm64: dts: rockchip: add rv1126b-evb2-v10-aov-dual-cam.dts and update Makefile

Change-Id: I397cfb1f76954c380c241b965f5839e4ecce8bc8
Signed-off-by: Leo Sun <leo.sun@rock-chips.com>
This commit is contained in:
Leo Sun
2025-06-25 11:09:17 +08:00
committed by Tao Huang
parent ed3b40c176
commit d08f47a2c4
2 changed files with 183 additions and 0 deletions

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@@ -385,6 +385,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nand.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-fastboot-spi-nor.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-spi-nor.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-aov-dual-cam.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-mcu-k350c4516t.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb

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@@ -0,0 +1,182 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1126b.dtsi"
#include "rv1126b-evb.dtsi"
#include "rv1126b-evb2-v10.dtsi"
#include "rv1126b-evb-dual-cam-4k.dtsi"
/ {
model = "Rockchip RV1126B EVB2 V10 Board";
compatible = "rockchip,rv1126b-evb2-v10", "rockchip,rv1126b";
};
&rockchip_suspend {
status = "okay";
rockchip,sleep-pin-config = <
(0
| RKPM_SLEEP_PIN0_EN
)
(0
| RKPM_SLEEP_PIN0_ACT_LOW
)
>;
rockchip,sleep-io-config = <
/* pmic_sleep */
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(0)
)
/* reset */
#if 0
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_NONE
| RKPM_IO_CFG_ID(1)
)
#endif
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(2)
)
(0
| RKPM_IO_CFG_PULL_NONE
| RKPM_IO_CFG_ID(3)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_UP
| RKPM_IO_CFG_ID(4)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(5)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(6)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_UP
| RKPM_IO_CFG_ID(7)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(8)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(9)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(10)
)
/* uart0 tx */
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(11)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(12)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(16)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(17)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_NONE
| RKPM_IO_CFG_ID(18)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_NONE
| RKPM_IO_CFG_ID(19)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(20)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(21)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(22)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(23)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(24)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(25)
)
>;
};
&sc850sl_0 {
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-stb = <1>;
};
&sc850sl_1 {
reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-stb = <1>;
};