Revert "Revert "net: phy: broadcom: Set proper 1000BaseX/SGMII interface mode for BCM54616S""
This reverts commit e444b4e1e9 as the kabi
can be updated at this point in time.
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I34471a1c4edc7c82c7602b85c595984c39d02e86
This commit is contained in:
Greg Kroah-Hartman
committed by
Todd Kjos
Todd Kjos
parent
15ba58936b
commit
ccd273758c
@@ -103,6 +103,64 @@ static int bcm54612e_config_init(struct phy_device *phydev)
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return 0;
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}
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static int bcm54616s_config_init(struct phy_device *phydev)
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{
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int rc, val;
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if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
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phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
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return 0;
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/* Ensure proper interface mode is selected. */
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/* Disable RGMII mode */
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val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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if (val < 0)
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return val;
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val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
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val |= MII_BCM54XX_AUXCTL_MISC_WREN;
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rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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val);
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if (rc < 0)
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return rc;
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/* Select 1000BASE-X register set (primary SerDes) */
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
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if (val < 0)
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return val;
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val |= BCM54XX_SHD_MODE_1000BX;
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rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
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if (rc < 0)
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return rc;
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/* Power down SerDes interface */
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rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
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if (rc < 0)
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return rc;
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/* Select proper interface mode */
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val &= ~BCM54XX_SHD_INTF_SEL_MASK;
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val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
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BCM54XX_SHD_INTF_SEL_SGMII :
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BCM54XX_SHD_INTF_SEL_GBIC;
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rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
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if (rc < 0)
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return rc;
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/* Power up SerDes interface */
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rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
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if (rc < 0)
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return rc;
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/* Select copper register set */
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val &= ~BCM54XX_SHD_MODE_1000BX;
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rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
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if (rc < 0)
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return rc;
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/* Power up copper interface */
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return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
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}
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/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
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static int bcm50610_a0_workaround(struct phy_device *phydev)
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{
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@@ -281,15 +339,17 @@ static int bcm54xx_config_init(struct phy_device *phydev)
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bcm54xx_adjust_rxrefclk(phydev);
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
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switch (BRCM_PHY_MODEL(phydev)) {
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case PHY_ID_BCM54210E:
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err = bcm54210e_config_init(phydev);
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if (err)
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return err;
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} else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
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break;
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case PHY_ID_BCM54612E:
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err = bcm54612e_config_init(phydev);
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if (err)
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return err;
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} else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
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break;
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case PHY_ID_BCM54616S:
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err = bcm54616s_config_init(phydev);
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break;
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case PHY_ID_BCM54810:
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/* For BCM54810, we need to disable BroadR-Reach function */
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val = bcm_phy_read_exp(phydev,
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BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
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@@ -297,9 +357,10 @@ static int bcm54xx_config_init(struct phy_device *phydev)
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err = bcm_phy_write_exp(phydev,
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BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
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val);
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if (err < 0)
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return err;
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break;
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}
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if (err)
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return err;
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bcm54xx_phydsp_config(phydev);
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@@ -478,7 +539,7 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
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static int bcm54616s_probe(struct phy_device *phydev)
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{
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int val, intf_sel;
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int val;
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
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if (val < 0)
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@@ -490,8 +551,7 @@ static int bcm54616s_probe(struct phy_device *phydev)
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* RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
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* support is still missing as of now.
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*/
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intf_sel = (val & BCM54XX_SHD_INTF_SEL_MASK) >> 1;
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if (intf_sel == 1) {
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if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
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val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
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if (val < 0)
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return val;
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@@ -136,6 +136,7 @@
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#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
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#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
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#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080
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#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
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#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
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#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
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@@ -222,6 +223,9 @@
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/* 11111: Mode Control Register */
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#define BCM54XX_SHD_MODE 0x1f
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#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
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#define BCM54XX_SHD_INTF_SEL_RGMII 0x02
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#define BCM54XX_SHD_INTF_SEL_SGMII 0x04
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#define BCM54XX_SHD_INTF_SEL_GBIC 0x06
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#define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
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/*
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