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FROMLIST: ARM: dts: rockchip: add support emac for RK3036

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This patch adds the emac device node for rk3036.
We need to let mac clock under the DPLL which is able to provide
the accurate 50MHz what mac_ref need, since that will cause some
unstable things if the cpufreq is working.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Bug: 27307957
Patchset: support emac for rk3036 dts.

(am from https://patchwork.kernel.org/patch/8186601/)
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: If4b618c6bf3b2640fbdb9cdf2ebc1b09f796841a
This commit is contained in:
zhengxing
2016-02-02 11:40:51 +08:00
committed by Caesar Wang
parent fb99df4137
commit 79f3c276bb
3 changed files with 83 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm/boot/dts/rk3036-evb.dts
View File

@@ -47,6 +47,17 @@
compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
phy = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&i2c1 {
status = "okay";
@@ -62,3 +73,15 @@
&uart2 {
status = "okay";
};
&pinctrl {
pcfg_output_high: pcfg-output-high {
output-high;
};
emac {
rmii_rst: rmii-rst {
rockchip,pins = <2 22 RK_FUNC_GPIO &pcfg_output_high>;
};
};
};

21
arch/arm/boot/dts/rk3036-kylin.dts
View File

@@ -112,6 +112,17 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
phy = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&emmc {
status = "okay";
};
@@ -384,6 +395,16 @@
};
&pinctrl {
pcfg_output_high: pcfg-output-high {
output-high;
};
emac {
rmii_rst: rmii-rst {
rockchip,pins = <2 22 RK_FUNC_GPIO &pcfg_output_high>;
};
};
leds {
led_ctl: led-ctl {
rockchip,pins = <2 30 RK_FUNC_GPIO &pcfg_pull_none>;

39
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -223,6 +223,27 @@
status = "disabled";
};
emac: ethernet@10200000 {
compatible = "rockchip,rk3036-emac", "snps,arc-emac";
reg = <0x10200000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
clock-names = "hclk", "macref", "macclk";
/*
* Fix the emac parent clock is DPLL instead of APLL.
* since that will cause some unstable things if the cpufreq
* is working. (e.g: the accurate 50MHz what mac_ref need)
*/
assigned-clocks = <&cru SCLK_MACPLL>;
assigned-clock-parents = <&cru PLL_DPLL>;
max-speed = <100>;
phy-mode = "rmii";
status = "disabled";
};
sdmmc: dwmmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -629,6 +650,24 @@
};
};
emac {
emac_xfer: emac-xfer {
rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
<2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
<2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
<2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
<2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
<2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
<2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
<2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
};
emac_mdio: emac-mdio {
rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
<2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,