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Merge commit 'ccc60a624971b61ccbe2780289b39fae1c2e88d2'

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* commit 'ccc60a624971b61ccbe2780289b39fae1c2e88d2':
  media: rockchip: vicap support to do reset in online mode
  media: rockchip: isp support to do reset in online mode
  arm64: dts: rockchip: rk3588 boards: Fix bitclock-inversion
  arm64: dts: rockchip: rk356x boards: Fix bitclock-inversion
  arm64: dts: rockchip: rk3528 boards: Fix bitclock-inversion
  arm64: dts: rockchip: rk3399-tve1205g: Fix bitclock-inversion
  arm64: dts: rockchip: rk3326-evb: Fix bitclock-inversion
  video: rockchip: mpp: Add uapi header
  soc: rockchip: tb_service: add memory-no-free property support

Change-Id: I068ca307ee0ec53eb570ce4f7fd5604c6bb796d8
This commit is contained in:
Tao Huang
2023-11-06 11:06:11 +08:00
parent 71f1b94ae2 ccc60a6249
commit 796ecb79e1
29 changed files with 182 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v10.dts
View File

@@ -130,7 +130,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11-i2s-dmic.dts
View File

@@ -140,7 +140,7 @@
compatible = "simple-audio-card";
status = "disabled";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v11.dts
View File

@@ -130,7 +130,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3326-evb-ai-va-v12.dts
View File

@@ -130,7 +130,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3399-tve1205g.dts
View File

@@ -166,7 +166,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi
View File

@@ -50,7 +50,7 @@
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
View File

@@ -49,7 +49,7 @@
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3566-box.dtsi
View File

@@ -42,7 +42,7 @@
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
View File

@@ -151,7 +151,7 @@
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3568-toybrick-sd0.dtsi
View File

@@ -18,7 +18,7 @@
status = "okay";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <512>;
simple-audio-card,name = "rockchip,bt";
#simple-audio-card,bitclock-master = <&sound2_master>;

2
arch/arm64/boot/dts/rockchip/rk3568-toybrick.dtsi
View File

@@ -169,7 +169,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
#simple-audio-card,bitclock-master = <&sound2_master>;

2
arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
View File

@@ -94,7 +94,7 @@
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts
View File

@@ -20,7 +20,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts
View File

@@ -19,7 +19,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts
View File

@@ -18,7 +18,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
View File

@@ -280,7 +280,7 @@
bt-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <1>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

2
arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
View File

@@ -92,7 +92,7 @@
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion = <0>;
simple-audio-card,bitclock-inversion;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,bt";
simple-audio-card,cpu {

29
drivers/media/platform/rockchip/cif/capture.c
View File

@@ -9002,6 +9002,15 @@ static void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq)
}
}
static void rkcif_toisp_set_stream(struct rkcif_device *dev, int on)
{
struct v4l2_subdev *sd = get_rkisp_sd(dev->sditf[0]);
if (sd)
v4l2_subdev_call(sd, core, ioctl,
RKISP_VICAP_CMD_SET_STREAM, &on);
}
static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
enum rkmodule_reset_src reset_src)
{
@@ -9108,6 +9117,9 @@ static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
}
}
if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
rkcif_toisp_set_stream(cif_dev, 1);
for (i = 0; i < j; i++) {
stream = resume_stream[i];
stream->fs_cnt_in_single_frame = 0;
@@ -9355,6 +9367,7 @@ static void rkcif_init_reset_work(struct rkcif_timer *timer)
timer->csi2_err_cnt_even = 0;
timer->csi2_err_fs_fe_cnt = 0;
timer->notifer_called_cnt = 0;
dev->is_toisp_reset = false;
for (i = 0; i < dev->num_channels; i++) {
stream = &dev->stream[i];
if (stream->state == RKCIF_STATE_STREAMING)
@@ -9364,10 +9377,10 @@ static void rkcif_init_reset_work(struct rkcif_timer *timer)
if (timer->is_ctrl_by_user) {
rkcif_send_reset_event(dev, timer->reset_src);
} else {
dev->reset_work.reset_src = timer->reset_src;
if (!schedule_work(&dev->reset_work.work))
v4l2_info(&dev->v4l2_dev,
"schedule reset work failed\n");
dev->reset_work.reset_src = timer->reset_src;
}
}
@@ -9382,6 +9395,15 @@ static int rkcif_detect_reset_event(struct rkcif_stream *stream,
int ret, is_reset = 0;
struct rkmodule_vicap_reset_info rst_info;
if (dev->is_toisp_reset) {
is_reset = 1;
timer->reset_src = RKCIF_RESET_SRC_ERR_ISP;
}
if (is_reset) {
rkcif_init_reset_work(timer);
return is_reset;
}
if (timer->last_buf_wakeup_cnt[stream->id] < stream->buf_wake_up_cnt &&
check_cnt == 0) {
@@ -9983,6 +10005,11 @@ static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
cur_time = ktime_get_ns();
stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
stream->readout.fs_timestamp = cur_time;
stream->buf_wake_up_cnt++;
if (stream->frame_idx % 2)
stream->fps_stats.frm0_timestamp = ktime_get_ns();
else
stream->fps_stats.frm1_timestamp = ktime_get_ns();
if (stream->cifdev->rdbk_debug &&
stream->frame_idx < 15)
v4l2_info(&priv->cif_dev->v4l2_dev,

2
drivers/media/platform/rockchip/cif/dev.c
View File

@@ -1134,6 +1134,7 @@ static int rkcif_pipeline_set_stream(struct rkcif_pipeline *p, bool on)
cif_dev->reset_watchdog_timer.is_triggered = false;
cif_dev->reset_watchdog_timer.is_running = false;
cif_dev->err_state_work.last_timestamp = 0;
cif_dev->is_toisp_reset = false;
for (i = 0; i < cif_dev->num_channels; i++)
cif_dev->reset_watchdog_timer.last_buf_wakeup_cnt[i] = 0;
cif_dev->reset_watchdog_timer.run_cnt = 0;
@@ -1218,6 +1219,7 @@ static int rkcif_pipeline_set_stream(struct rkcif_pipeline *p, bool on)
cif_dev->is_start_hdr = true;
cif_dev->reset_watchdog_timer.is_triggered = false;
cif_dev->reset_watchdog_timer.is_running = false;
cif_dev->is_toisp_reset = false;
for (i = 0; i < cif_dev->num_channels; i++)
cif_dev->reset_watchdog_timer.last_buf_wakeup_cnt[i] = 0;
cif_dev->reset_watchdog_timer.run_cnt = 0;

1
drivers/media/platform/rockchip/cif/dev.h
View File

@@ -883,6 +883,7 @@ struct rkcif_device {
bool is_support_tools;
bool is_rtt_suspend;
bool sensor_state_change;
bool is_toisp_reset;
int rdbk_debug;
struct rkcif_sync_cfg sync_cfg;
int sditf_cnt;

9
drivers/media/platform/rockchip/cif/subdev-itf.c
View File

@@ -378,6 +378,12 @@ static long sditf_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
rkcif_stream_suspend(cif_dev, RKCIF_RESUME_ISP);
}
break;
case RKISP_VICAP_CMD_SET_RESET:
if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE) {
cif_dev->is_toisp_reset = true;
return 0;
}
break;
default:
break;
}
@@ -435,6 +441,9 @@ static long sditf_compat_ioctl32(struct v4l2_subdev *sd,
return -EFAULT;
ret = sditf_ioctl(sd, cmd, &on);
return ret;
case RKISP_VICAP_CMD_SET_RESET:
ret = sditf_ioctl(sd, cmd, NULL);
return ret;
default:
break;
}

1
drivers/media/platform/rockchip/isp/dev.h
View File

@@ -81,6 +81,7 @@ enum rkisp_isp_state {
ISP_START = BIT(9),
ISP_ERROR = BIT(10),
ISP_MIPI_ERROR = BIT(11),
ISP_CIF_RESET = BIT(12),
};
enum rkisp_isp_inp {

6
drivers/media/platform/rockchip/isp/isp_external.h
View File

@@ -16,6 +16,12 @@
#define RKISP_VICAP_CMD_QUICK_STREAM \
_IOW('V', BASE_VIDIOC_PRIVATE + 3, int)
#define RKISP_VICAP_CMD_SET_RESET \
_IOW('V', BASE_VIDIOC_PRIVATE + 4, int)
#define RKISP_VICAP_CMD_SET_STREAM \
_IOW('V', BASE_VIDIOC_PRIVATE + 5, int)
#define RKISP_VICAP_BUF_CNT 3
#define RKISP_VICAP_BUF_CNT_MAX 8
#define RKISP_RX_BUF_POOL_MAX (RKISP_VICAP_BUF_CNT_MAX * 3)

33
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -1218,8 +1218,11 @@ static void rkisp_restart_monitor(struct work_struct *work)
/* isp stop to exit
* isp err to reset
* mipi err wait isp idle, then reset
* online vicap if isp err, notify vicap reset, then vicap notify isp reset
* by ioctl RKISP_VICAP_CMD_SET_STREAM
*/
if (monitor->state & ISP_STOP ||
monitor->state & ISP_CIF_RESET ||
(ret && !(monitor->state & ISP_ERROR)) ||
(!ret &&
monitor->state & ISP_FRAME_END &&
@@ -1268,10 +1271,22 @@ static void rkisp_restart_monitor(struct work_struct *work)
/* restart isp */
isp = hw->isp[hw->cur_dev_id];
ret = rkisp_reset_handle(isp);
if (ret) {
monitor->is_en = false;
break;
if (!IS_HDR_RDBK(isp->hdr.op_mode) && isp->isp_ver >= ISP_V30) {
struct v4l2_subdev *remote = NULL;
struct v4l2_subdev *isp_subdev = NULL;
isp_subdev = &(isp->isp_sdev.sd);
remote = get_remote_sensor(isp_subdev);
v4l2_subdev_call(remote, core, ioctl,
RKISP_VICAP_CMD_SET_RESET, NULL);
monitor->state |= ISP_CIF_RESET;
continue;
} else {
ret = rkisp_reset_handle(isp);
if (ret) {
monitor->is_en = false;
break;
}
}
for (i = 0; i < hw->dev_num; i++) {
@@ -3493,6 +3508,13 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
rkisp_hw_enum_isp_size(isp_dev->hw_dev);
}
break;
case RKISP_VICAP_CMD_SET_STREAM:
ret = rkisp_reset_handle(isp_dev);
if (!ret) {
if (isp_dev->hw_dev->monitor.state & ISP_CIF_RESET)
isp_dev->hw_dev->monitor.state &= ~ISP_CIF_RESET;
}
break;
default:
ret = -ENOIOCTLCMD;
}
@@ -3595,6 +3617,9 @@ static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
ret = rkisp_ioctl(sd, cmd, NULL);
break;
case RKISP_VICAP_CMD_SET_STREAM:
ret = rkisp_ioctl(sd, cmd, NULL);
break;
default:
ret = -ENOIOCTLCMD;
}

6
drivers/soc/rockchip/rockchip_thunderboot_service.c
View File

@@ -24,6 +24,7 @@ struct rk_tb_serv {
struct reset_control *rsts;
phys_addr_t mem_start;
size_t mem_size;
bool mem_no_free;
};
static atomic_t mcu_done = ATOMIC_INIT(0);
@@ -89,7 +90,8 @@ static void do_mcu_done(struct rk_tb_serv *serv)
start = phys_to_virt(serv->mem_start);
end = start + serv->mem_size;
free_reserved_area(start, end, -1, "rtos");
if (!serv->mem_no_free)
free_reserved_area(start, end, -1, "rtos");
spin_lock(&lock);
if (atomic_read(&mcu_done)) {
@@ -150,6 +152,8 @@ static int rk_tb_serv_probe(struct platform_device *pdev)
if (IS_ERR(serv->rsts) && PTR_ERR(serv->rsts) == -EPROBE_DEFER)
return -EPROBE_DEFER;
serv->mem_no_free = device_property_read_bool(&pdev->dev, "memory-no-free");
platform_set_drvdata(pdev, serv);
mbox_cl = &serv->mbox_cl;

14
drivers/video/rockchip/mpp/mpp_common.c
View File

@@ -36,12 +36,6 @@
#include "mpp_common.h"
#include "mpp_iommu.h"
/* Use 'v' as magic number */
#define MPP_IOC_MAGIC 'v'
#define MPP_IOC_CFG_V1 _IOW(MPP_IOC_MAGIC, 1, unsigned int)
#define MPP_IOC_CFG_V2 _IOW(MPP_IOC_MAGIC, 2, unsigned int)
/* input parmater structure for version 1 */
struct mpp_msg_v1 {
__u32 cmd;
@@ -51,14 +45,6 @@ struct mpp_msg_v1 {
__u64 data_ptr;
};
#define MPP_BAT_MSG_DONE (0x00000001)
struct mpp_bat_msg {
__u64 flag;
__u32 fd;
__s32 ret;
};
#ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
const char *mpp_device_name[MPP_DEVICE_BUTT] = {
[MPP_DEVICE_VDPU1] = "VDPU1",

56
drivers/video/rockchip/mpp/mpp_common.h
View File

@@ -24,6 +24,7 @@
#include <linux/poll.h>
#include <linux/platform_device.h>
#include <soc/rockchip/pm_domains.h>
#include <uapi/linux/rk-mpp.h>
#define MHZ (1000 * 1000)
#define MPP_WORK_TIMEOUT_DELAY (500)
@@ -31,13 +32,6 @@
#define MPP_MAX_MSG_NUM (16)
#define MPP_MAX_REG_TRANS_NUM (60)
#define MPP_MAX_TASK_CAPACITY (16)
/* define flags for mpp_request */
#define MPP_FLAGS_MULTI_MSG (0x00000001)
#define MPP_FLAGS_LAST_MSG (0x00000002)
#define MPP_FLAGS_REG_FD_NO_TRANS (0x00000004)
#define MPP_FLAGS_SCL_FD_NO_TRANS (0x00000008)
#define MPP_FLAGS_REG_NO_OFFSET (0x00000010)
#define MPP_FLAGS_SECURE_MODE (0x00010000)
/* grf mask for get value */
#define MPP_GRF_VAL_MASK (0xFFFF)
@@ -93,45 +87,6 @@ enum MPP_DRIVER_TYPE {
MPP_DRIVER_BUTT,
};
/**
* Command type: keep the same as user space
*/
enum MPP_DEV_COMMAND_TYPE {
MPP_CMD_QUERY_BASE = 0,
MPP_CMD_QUERY_HW_SUPPORT = MPP_CMD_QUERY_BASE + 0,
MPP_CMD_QUERY_HW_ID = MPP_CMD_QUERY_BASE + 1,
MPP_CMD_QUERY_CMD_SUPPORT = MPP_CMD_QUERY_BASE + 2,
MPP_CMD_QUERY_BUTT,
MPP_CMD_INIT_BASE = 0x100,
MPP_CMD_INIT_CLIENT_TYPE = MPP_CMD_INIT_BASE + 0,
MPP_CMD_INIT_DRIVER_DATA = MPP_CMD_INIT_BASE + 1,
MPP_CMD_INIT_TRANS_TABLE = MPP_CMD_INIT_BASE + 2,
MPP_CMD_INIT_BUTT,
MPP_CMD_SEND_BASE = 0x200,
MPP_CMD_SET_REG_WRITE = MPP_CMD_SEND_BASE + 0,
MPP_CMD_SET_REG_READ = MPP_CMD_SEND_BASE + 1,
MPP_CMD_SET_REG_ADDR_OFFSET = MPP_CMD_SEND_BASE + 2,
MPP_CMD_SET_RCB_INFO = MPP_CMD_SEND_BASE + 3,
MPP_CMD_SET_SESSION_FD = MPP_CMD_SEND_BASE + 4,
MPP_CMD_SEND_BUTT,
MPP_CMD_POLL_BASE = 0x300,
MPP_CMD_POLL_HW_FINISH = MPP_CMD_POLL_BASE + 0,
MPP_CMD_POLL_HW_IRQ = MPP_CMD_POLL_BASE + 1,
MPP_CMD_POLL_BUTT,
MPP_CMD_CONTROL_BASE = 0x400,
MPP_CMD_RESET_SESSION = MPP_CMD_CONTROL_BASE + 0,
MPP_CMD_TRANS_FD_TO_IOVA = MPP_CMD_CONTROL_BASE + 1,
MPP_CMD_RELEASE_FD = MPP_CMD_CONTROL_BASE + 2,
MPP_CMD_SEND_CODEC_INFO = MPP_CMD_CONTROL_BASE + 3,
MPP_CMD_CONTROL_BUTT,
MPP_CMD_BUTT,
};
enum MPP_CLOCK_MODE {
CLK_MODE_BASE = 0,
CLK_MODE_DEFAULT = CLK_MODE_BASE,
@@ -195,15 +150,6 @@ struct mpp_dma_session;
struct mpp_taskqueue;
struct iommu_domain;
/* data common struct for parse out */
struct mpp_request {
__u32 cmd;
__u32 flags;
__u32 size;
__u32 offset;
void __user *data;
};
/* struct use to collect task set and poll message */
struct mpp_task_msgs {
/* for ioctl msgs bat process */

1
include/uapi/linux/rk-camera-module.h
View File

@@ -638,6 +638,7 @@ enum rkmodule_reset_src {
RKICF_RESET_SRC_ERR_CUTOFF,
RKCIF_RESET_SRC_ERR_HOTPLUG,
RKCIF_RESET_SRC_ERR_APP,
RKCIF_RESET_SRC_ERR_ISP,
};
struct rkmodule_vicap_reset_info {

82
include/uapi/linux/rk-mpp.h Normal file
View File

@@ -0,0 +1,82 @@
/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */
/*
* Rockchip mpp driver
* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
*/
#ifndef _UAPI_RK_MPP_H
#define _UAPI_RK_MPP_H
#include <linux/types.h>
/* Use 'v' as magic number */
#define MPP_IOC_MAGIC 'v'
#define MPP_IOC_CFG_V1 _IOW(MPP_IOC_MAGIC, 1, unsigned int)
#define MPP_IOC_CFG_V2 _IOW(MPP_IOC_MAGIC, 2, unsigned int)
/**
* Command type: keep the same as user space
*/
enum MPP_DEV_COMMAND_TYPE {
MPP_CMD_QUERY_BASE = 0,
MPP_CMD_QUERY_HW_SUPPORT = MPP_CMD_QUERY_BASE + 0,
MPP_CMD_QUERY_HW_ID = MPP_CMD_QUERY_BASE + 1,
MPP_CMD_QUERY_CMD_SUPPORT = MPP_CMD_QUERY_BASE + 2,
MPP_CMD_QUERY_BUTT,
MPP_CMD_INIT_BASE = 0x100,
MPP_CMD_INIT_CLIENT_TYPE = MPP_CMD_INIT_BASE + 0,
MPP_CMD_INIT_DRIVER_DATA = MPP_CMD_INIT_BASE + 1,
MPP_CMD_INIT_TRANS_TABLE = MPP_CMD_INIT_BASE + 2,
MPP_CMD_INIT_BUTT,
MPP_CMD_SEND_BASE = 0x200,
MPP_CMD_SET_REG_WRITE = MPP_CMD_SEND_BASE + 0,
MPP_CMD_SET_REG_READ = MPP_CMD_SEND_BASE + 1,
MPP_CMD_SET_REG_ADDR_OFFSET = MPP_CMD_SEND_BASE + 2,
MPP_CMD_SET_RCB_INFO = MPP_CMD_SEND_BASE + 3,
MPP_CMD_SET_SESSION_FD = MPP_CMD_SEND_BASE + 4,
MPP_CMD_SEND_BUTT,
MPP_CMD_POLL_BASE = 0x300,
MPP_CMD_POLL_HW_FINISH = MPP_CMD_POLL_BASE + 0,
MPP_CMD_POLL_HW_IRQ = MPP_CMD_POLL_BASE + 1,
MPP_CMD_POLL_BUTT,
MPP_CMD_CONTROL_BASE = 0x400,
MPP_CMD_RESET_SESSION = MPP_CMD_CONTROL_BASE + 0,
MPP_CMD_TRANS_FD_TO_IOVA = MPP_CMD_CONTROL_BASE + 1,
MPP_CMD_RELEASE_FD = MPP_CMD_CONTROL_BASE + 2,
MPP_CMD_SEND_CODEC_INFO = MPP_CMD_CONTROL_BASE + 3,
MPP_CMD_CONTROL_BUTT,
MPP_CMD_BUTT,
};
/* define flags for mpp_request */
#define MPP_FLAGS_MULTI_MSG (0x00000001)
#define MPP_FLAGS_LAST_MSG (0x00000002)
#define MPP_FLAGS_REG_FD_NO_TRANS (0x00000004)
#define MPP_FLAGS_SCL_FD_NO_TRANS (0x00000008)
#define MPP_FLAGS_REG_NO_OFFSET (0x00000010)
#define MPP_FLAGS_SECURE_MODE (0x00010000)
/* data common struct for parse out */
struct mpp_request {
__u32 cmd;
__u32 flags;
__u32 size;
__u32 offset;
void __user *data;
};
#define MPP_BAT_MSG_DONE (0x00000001)
struct mpp_bat_msg {
__u64 flag;
__u32 fd;
__s32 ret;
};
#endif /* _UAPI_RK_MPP_H */