mirros/rockchip-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: rockchip: rk3506: Use MUXTBL for MCLK_SAI

Browse Source 
Change-Id: I590ae0788ab9e064563284d157078b8a0bbcb349
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2025-01-08 19:23:20 +08:00
committed by Tao Huang
parent 9b5850c977
commit 75588ef133
1 changed files with 19 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
drivers/clk/rockchip/clk-rk3506.c
View File

@@ -131,7 +131,7 @@ PNAME(clk_can_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_ga
PNAME(clk_pdm_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
"clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
"clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "clk_gpll_div" };
PNAME(mclk_sai_asrc_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
PNAME(mclk_spdif_asrc_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
"clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
"clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in" };
PNAME(lrck_asrc_parents_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3", "mclk_spdiftx", "clk_spdifrx_to_asrc", "clkout_pdm",
@@ -147,6 +147,9 @@ PNAME(clk_32k_parents_p) = { "xin32k", "clk_32k_rc", "clk_32k_frac" };
PNAME(clk_ref_phy_pmu_mux_parents_p) = { "xin24m", "clk_ref_phy_pll" };
PNAME(clk_vpll_ref_parents_p) = { "xin24m", "clk_pll_ref_io" };
PNAME(mux_armclk_p) = { "armclk_pll", "clk_core_pvtpll" };
PNAME(mclk_sai_parents_p) = { "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
"clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" };
static u32 sai_src_mux_idx[] = { 9, 10, 11, 12, 0, 1, 2, 3, 4, 5, 6, 7, 8 };
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
@@ -505,7 +508,7 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
COMPOSITE(CLKOUT_PDM, "clkout_pdm", clk_pdm_parents_p, 0,
RK3506_CLKSEL_CON(38), 10, 4, MFLAGS, 0, 10, DFLAGS,
RK3506_CLKGATE_CON(13), 10, GFLAGS),
COMPOSITE(MCLK_SPDIFTX, "mclk_spdiftx", mclk_sai_asrc_parents_p, 0,
COMPOSITE(MCLK_SPDIFTX, "mclk_spdiftx", mclk_spdif_asrc_parents_p, 0,
RK3506_CLKSEL_CON(39), 5, 4, MFLAGS, 0, 5, DFLAGS,
RK3506_CLKGATE_CON(13), 11, GFLAGS),
GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_lsperi_root", 0,
@@ -515,15 +518,15 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
COMPOSITE(MCLK_SPDIFRX, "mclk_spdifrx", gpll_v0pll_v1pll_g_parents_p, 0,
RK3506_CLKSEL_CON(39), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3506_CLKGATE_CON(13), 14, GFLAGS),
COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai_asrc_parents_p, 0,
RK3506_CLKSEL_CON(40), 8, 4, MFLAGS, 0, 8, DFLAGS,
COMPOSITE_MUXTBL(MCLK_SAI0, "mclk_sai0", mclk_sai_parents_p, 0,
RK3506_CLKSEL_CON(40), 8, 4, MFLAGS, sai_src_mux_idx, 0, 8, DFLAGS,
RK3506_CLKGATE_CON(13), 15, GFLAGS),
GATE(HCLK_SAI0, "hclk_sai0", "hclk_lsperi_root", 0,
RK3506_CLKGATE_CON(14), 0, GFLAGS),
GATE(MCLK_OUT_SAI0, "mclk_out_sai0", "mclk_sai0", 0,
RK3506_CLKGATE_CON(14), 1, GFLAGS),
COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai_asrc_parents_p, 0,
RK3506_CLKSEL_CON(41), 8, 4, MFLAGS, 0, 8, DFLAGS,
COMPOSITE_MUXTBL(MCLK_SAI1, "mclk_sai1", mclk_sai_parents_p, 0,
RK3506_CLKSEL_CON(41), 8, 4, MFLAGS, sai_src_mux_idx, 0, 8, DFLAGS,
RK3506_CLKGATE_CON(14), 2, GFLAGS),
GATE(HCLK_SAI1, "hclk_sai1", "hclk_lsperi_root", 0,
RK3506_CLKGATE_CON(14), 3, GFLAGS),
@@ -543,16 +546,16 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
RK3506_CLKGATE_CON(14), 9, GFLAGS),
GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "pclk_lsperi_root", CLK_IS_CRITICAL,
RK3506_CLKGATE_CON(14), 10, GFLAGS),
COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mclk_sai_asrc_parents_p, 0,
COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mclk_spdif_asrc_parents_p, 0,
RK3506_CLKSEL_CON(46), 0, 4, MFLAGS,
RK3506_CLKGATE_CON(16), 0, GFLAGS),
COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mclk_sai_asrc_parents_p, 0,
COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mclk_spdif_asrc_parents_p, 0,
RK3506_CLKSEL_CON(46), 4, 4, MFLAGS,
RK3506_CLKGATE_CON(16), 1, GFLAGS),
COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mclk_sai_asrc_parents_p, 0,
COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mclk_spdif_asrc_parents_p, 0,
RK3506_CLKSEL_CON(46), 8, 4, MFLAGS,
RK3506_CLKGATE_CON(16), 2, GFLAGS),
COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mclk_sai_asrc_parents_p, 0,
COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mclk_spdif_asrc_parents_p, 0,
RK3506_CLKSEL_CON(46), 12, 4, MFLAGS,
RK3506_CLKGATE_CON(16), 3, GFLAGS),
COMPOSITE_NODIV(LRCK_ASRC0_SRC, "lrck_asrc0_src", lrck_asrc_parents_p, 0,
@@ -603,15 +606,15 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
RK3506_CLKGATE_CON(18), 0, GFLAGS),
GATE(CLK_MAC1, "clk_mac1", "clk_mac_root", 0,
RK3506_CLKGATE_CON(18), 1, GFLAGS),
COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai_asrc_parents_p, 0,
RK3506_CLKSEL_CON(51), 8, 4, MFLAGS, 0, 8, DFLAGS,
COMPOSITE_MUXTBL(MCLK_SAI2, "mclk_sai2", mclk_sai_parents_p, 0,
RK3506_CLKSEL_CON(51), 8, 4, MFLAGS, sai_src_mux_idx, 0, 8, DFLAGS,
RK3506_CLKGATE_CON(18), 2, GFLAGS),
GATE(HCLK_SAI2, "hclk_sai2", "hclk_hsperi_root", 0,
RK3506_CLKGATE_CON(18), 3, GFLAGS),
GATE(MCLK_OUT_SAI2, "mclk_out_sai2", "mclk_sai2", 0,
RK3506_CLKGATE_CON(18), 4, GFLAGS),
COMPOSITE(MCLK_SAI3_SRC, "mclk_sai3_src", mclk_sai_asrc_parents_p, 0,
RK3506_CLKSEL_CON(52), 8, 4, MFLAGS, 0, 8, DFLAGS,
COMPOSITE_MUXTBL(MCLK_SAI3_SRC, "mclk_sai3_src", mclk_sai_parents_p, 0,
RK3506_CLKSEL_CON(52), 8, 4, MFLAGS, sai_src_mux_idx, 0, 8, DFLAGS,
RK3506_CLKGATE_CON(18), 5, GFLAGS),
GATE(HCLK_SAI3, "hclk_sai3", "hclk_hsperi_root", 0,
RK3506_CLKGATE_CON(18), 6, GFLAGS),
@@ -619,8 +622,8 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
RK3506_CLKGATE_CON(18), 7, GFLAGS),
GATE(MCLK_OUT_SAI3, "mclk_out_sai3", "mclk_sai3_src", 0,
RK3506_CLKGATE_CON(18), 8, GFLAGS),
COMPOSITE(MCLK_SAI4_SRC, "mclk_sai4_src", mclk_sai_asrc_parents_p, 0,
RK3506_CLKSEL_CON(53), 8, 4, MFLAGS, 0, 8, DFLAGS,
COMPOSITE_MUXTBL(MCLK_SAI4_SRC, "mclk_sai4_src", mclk_sai_parents_p, 0,
RK3506_CLKSEL_CON(53), 8, 4, MFLAGS, sai_src_mux_idx, 0, 8, DFLAGS,
RK3506_CLKGATE_CON(18), 9, GFLAGS),
GATE(HCLK_SAI4, "hclk_sai4", "hclk_hsperi_root", 0,
RK3506_CLKGATE_CON(18), 10, GFLAGS),