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isp11: rockchip: adjust the calculation for isp clk

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per isp clk cycle one Byte, don't reserved 20%.

Change-Id: Ibb09a1d9bb31643c8e89b8be67ccf4a1c28a6ac6
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
cyw
2017-08-25 09:32:03 +08:00
committed by Tao Huang
parent 248b20b009
commit 6c04d006ae
1 changed files with 3 additions and 3 deletions
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6
drivers/media/platform/rk-isp11/cif_isp11_rv1108.c
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@@ -271,18 +271,18 @@ static int soc_clk_disable(void)
static int soc_isp_clk_cfg(int *data_rate)
{
int isp_clk[] = {396, 480, 594};
int isp_clk[] = {400, 480, 594};
int tmp, i;
struct cif_isp11_clk_rst_rv1108 *clk_rst = &rv1108->clk_rst;
tmp = (*data_rate * 10) >> 6;
tmp = *data_rate >> 3;
for (i = 0; i < ARRAY_SIZE(isp_clk); i++)
if (tmp <= isp_clk[i])
break;
if (i == ARRAY_SIZE(isp_clk))
i--;
if (isp_clk[i] > 396)
if (isp_clk[i] > 400)
pr_warn("rv1108 isp signoff is 360MHz, using %dMHz maybe unstable\n",
isp_clk[i]);