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clk: rockchip: rv1106: Add pll frac freq for audio

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This patch add pll frac freq around 1G for audio product,
which will do fine tune pll for async clk situation,
such as BT, UAC.

Because we have no much more PLLs, and much more devices
share the same PLL, so, we should setup around 1G to serve
all the devices.

PLLs in rv1106:

  APLL: CPU
  DPLL: DDR
  GPLL: DEVICES
  CPLL: DEVICES

  GPLL: 1188MHz
  CPLL: 1000MHz

* PLLs support frac mode:

  GPLL
  DPLL

So, the only way to use audio pll frac freq is to switch to
use GPLL. and switch the role of GPLL and CPLL.

  GPLL: audio frac freq (~1G)
  CPLL: 1188MHz

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: If26f464ac88cd21195db14084f8b4e9ffb457890
This commit is contained in:
Sugar Zhang
2022-07-13 08:47:16 +08:00
committed by Tao Huang
parent 01dd2b51d5
commit 1fd942ea8b
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk-rv1106.c
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@@ -88,7 +88,9 @@ static struct rockchip_pll_rate_table rv1106_pll_rates[] = {
RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(993484800, 1, 124, 3, 1, 0, 3113851),
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE(983040000, 1, 81, 2, 1, 0, 15435038),
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),