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Revert "rk3368 dts: add ddr timing node in rk3368.dtsi"

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This reverts commit 8be554a502.

Remove unused driver.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I229ef6acb813f640f6b7f65e06d4d71a49e52839
This commit is contained in:
Tao Huang
2023-02-24 20:16:13 +08:00
parent ac127f231b
commit 085b39ca18
2 changed files with 0 additions and 160 deletions
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80
Documentation/devicetree/bindings/dram/rk3368_dram_timing.txt
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* rk3368 dram default timing is at arch/arm64/boot/dts/rk3368_dram_default_timing.dtsi
Required properties:
- compatible : Should be "rockchip,ddr-timing"
- dram_spd_bin : value is defined at include/dt-bindings/clock/ddr.h
it select ddr3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected
according to "Speed Bin" in ddr3 datasheet, DO NOT use smaller "Speed Bin" than
ddr3 exactly is.
- sr_idle : configure the SR_IDLE value, defined the selfrefresh idle period,
memories are places into self-refresh mode if bus is idle for SR_IDLE*32 DFI
clocks (DFI clocks freq is half of dram's clocks), defaule value is "1"
- pd_idle : config the PD_IDLE value, defined the power-down idle period, memories
are places into power-down mode if bus is idle for PD_IDLE DFI clocks.
- dram_dll_disb_freq : it's defined the DDR3 dll bypass frequency in MHz (Mega Hz),
when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3 dll will bypssed
note: if dll was bypassed, the odt also stop working.
- phy_dll_disb_freq : defined the PHY dll bypass frequency in MHz (Mega Hz),
when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll will bypssed
note: phy dll and phy odt are independent
- dram_odt_disb_freq : defined the DDR3 and LPDDR3 odt disable frequency in
MHz (Mega Hz), when ddr frequency less then DRAM_ODT_DISB_FREQ, the DDR3
and LPDDR3 ODT are disabled.
- phy_odt_disb_freq : defined the PHY odt disable frequency in MHz (Mega Hz),
when ddr frequency less then PHY_ODT_DISB_FREQ, the PHY ODT are disabled.
- ddr3_drv : define the DDR3 driver stength in ohm, default value is DDR3_DS_40
- ddr3_odt : define the DDR3 ODT in ohm, default value is DDR3_ODT_120
- lpddr3_drv : define the lPDDR3 driver stength in ohm, default value is LP3_DS_34
- lpddr3_odt : define the LPDDR3 ODT in ohm, default value is LP3_ODT_240
- lpddr2_drv : define the LPDDR2 driver stength in ohm, default value is LP2_DS_34
- phy_clk_drv : define the phy clocks driver strength in ohm, default value is
PHY_RON_45ohm
- phy_cmd_drv : define the phy commands driver strength in ohm, default value is
PHY_RON_34ohm
- phy_dqs_drv : define the phy dqs and dq driver strength in ohm, default value is
PHY_RON_34ohm
- phy_odt : define the phy odt in ohm, default value isPHY_RTT_279ohm
- ddr_2t : define the uptcl CMD/CLK 2T mode, default value is ENABLE_DDR_2T.
the driver strength and odt value are defined at include/dt-bindings/dram/rockchip,rk3368.h
Example:
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
dram_spd_bin = <DDR3_DEFAULT>;
sr_idle = <1>;
pd_idle = <0x20>;
dram_dll_disb_freq = <300>;
phy_dll_disb_freq = <400>;
dram_odt_disb_freq = <333>;
phy_odt_disb_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
lpddr2_drv = <LP2_DS_34ohm>;/*lpddr2 not supported odt*/
phy_clk_drv = <PHY_RON_45ohm>;
phy_cmd_drv = <PHY_RON_34ohm>;
phy_dqs_drv = <PHY_RON_34ohm>;
phy_odt = <PHY_RTT_279ohm>;
ddr_2t = <ENABLE_DDR_2T>;
};
};

80
include/dt-bindings/dram/rockchip,rk3368.h
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/*
*
* Copyright (C) 2011-2014 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H
#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H
#define DDR3_DS_34ohm (1<<1)
#define DDR3_DS_40ohm (0x0)
#define LP2_DS_34ohm (0x1)
#define LP2_DS_40ohm (0x2)
#define LP2_DS_48ohm (0x3)
#define LP2_DS_60ohm (0x4)
#define LP2_DS_68_6ohm (0x5)/*optional*/
#define LP2_DS_80ohm (0x6)
#define LP2_DS_120ohm (0x7)/*optional*/
#define LP3_DS_34ohm (0x1)
#define LP3_DS_40ohm (0x2)
#define LP3_DS_48ohm (0x3)
#define LP3_DS_60ohm (0x4)
#define LP3_DS_80ohm (0x6)
#define LP3_DS_34D_40U (0x9)
#define LP3_DS_40D_48U (0xa)
#define LP3_DS_34D_48U (0xb)
#define DDR3_ODT_DIS (0)
#define DDR3_ODT_40ohm ((1<<2)|(1<<6))
#define DDR3_ODT_60ohm (1<<2)
#define DDR3_ODT_120ohm (1<<6)
#define LP3_ODT_DIS (0)
#define LP3_ODT_60ohm (1)
#define LP3_ODT_120ohm (2)
#define LP3_ODT_240ohm (3)
#define PHY_RON_DISABLE (0)
#define PHY_RON_272ohm (1)
#define PHY_RON_135ohm (2)
#define PHY_RON_91ohm (3)
#define PHY_RON_38ohm (7)
#define PHY_RON_68ohm (8)
#define PHY_RON_54ohm (9)
#define PHY_RON_45ohm (10)
#define PHY_RON_39ohm (11)
#define PHY_RON_34ohm (12)
#define PHY_RON_30ohm (13)
#define PHY_RON_27ohm (14)
#define PHY_RON_25ohm (15)
#define PHY_RTT_DISABLE (0)
#define PHY_RTT_1116ohm (1)
#define PHY_RTT_558ohm (2)
#define PHY_RTT_372ohm (3)
#define PHY_RTT_279ohm (4)
#define PHY_RTT_223ohm (5)
#define PHY_RTT_186ohm (6)
#define PHY_RTT_159ohm (7)
#define PHY_RTT_139ohm (8)
#define PHY_RTT_124ohm (9)
#define PHY_RTT_112ohm (10)
#define PHY_RTT_101ohm (11)
#define PHY_RTT_93ohm (12)
#define PHY_RTT_86ohm (13)
#define PHY_RTT_80ohm (14)
#define PHY_RTT_74ohm (15)
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/