dcb117ae9b
Change-Id: I48c3fdbae620196abeef769f0b217be4ade0a6dc Signed-off-by: Jiahang Zheng <jiahang.zheng@rock-chips.com>
64 lines
1.3 KiB
Plaintext
64 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/soc/rockchip-amp.h>
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/ {
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rockchip_amp: rockchip-amp {
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compatible = "rockchip,amp";
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clocks = <&cru TCLK_WDT_HPMCU>, <&cru PCLK_WDT_HPMCU>,
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<&cru HCLK_CACHE>, <&cru CLK_HPMCU>,
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<&cru CLK_HPMCU_RTC>, <&cru PCLK_HPMCU_INTMUX>,
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<&cru SCLK_UART4>, <&cru PCLK_UART4>, <&cru PCLK_HPMCU_MAILBOX>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart4m2_xfer_pins>;
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status = "okay";
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};
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reserved-memory {
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/* hpmcu address */
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hpmcu_reserved: hpmcu@48c02000 {
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reg = <0x48c02000 0x3a000>;
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no-map;
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};
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rpmsg_reserved: rpmsg@48c3c000 {
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reg = <0x48c3c000 0x10000>;
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no-map;
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};
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rpmsg_dma_reserved: rpmsg-dma@48c4c000 {
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compatible = "shared-dma-pool";
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reg = <0x48c4c000 0x10000>;
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no-map;
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};
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};
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rpmsg: rpmsg@48c3c000 {
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compatible = "rockchip,rpmsg";
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mbox-names = "rpmsg-rx", "rpmsg-tx";
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mboxes = <&hpmcu_mbox0 0 &hpmcu_mbox3 0>;
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rockchip,vdev-nums = <1>;
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/* hpmcu: link-id 0x03; */
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rockchip,link-id = <0x03>;
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reg = <0x48c3c000 0x10000>;
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memory-region = <&rpmsg_dma_reserved>;
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status = "okay";
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};
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};
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&hpmcu_mbox0 {
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rockchip,txpoll-period-ms = <1>;
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status = "okay";
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};
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&hpmcu_mbox3 {
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rockchip,txpoll-period-ms = <1>;
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status = "okay";
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};
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