72d459a462
Change-Id: Ib1908adacedb69836159179f8226d6a4e0202550 Signed-off-by: Liang Chen <cl@rock-chips.com>
88 lines
2.1 KiB
Plaintext
88 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*/
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/delete-node/ &cpu_l0;
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/delete-node/ &cpu_l1;
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/delete-node/ &cpu_l2;
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/delete-node/ &cpu_l3;
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/ {
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cpus {
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cpu_l0: cpu@000 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&scmi_clk ARMCLK_L>;
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operating-points-v2 = <&cluster0_opp_table>;
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#cooling-cells = <2>;
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dynamic-power-coefficient = <120>;
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cpu-idle-states = <&CPU_SLEEP>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l>;
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};
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cpu_l1: cpu@001 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&scmi_clk ARMCLK_L>;
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operating-points-v2 = <&cluster0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l>;
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};
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cpu_l2: cpu@002 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&scmi_clk ARMCLK_L>;
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operating-points-v2 = <&cluster0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l>;
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};
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cpu_l3: cpu@003 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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capacity-dmips-mhz = <485>;
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clocks = <&scmi_clk ARMCLK_L>;
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operating-points-v2 = <&cluster0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2_cache_l>;
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};
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};
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};
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