90714f7ed7
[ Upstream commitcf9ae4a007] In pre-production prototypes (of which I only know one person having one, Peter Geis), GPIO0 pin A5 was tied to the SDMMC power enable pin on the CM4 connector. On all production models, this is not the case; instead, this pin is used for the nEXTRST signal, and the SDMMC power enable pin is always pulled high. Since everyone currently using the SOQuartz device trees will want this change, it is made to the tree without splitting the trees into two separate ones of which users will then inevitably choose the wrong one. This fixes USB and PCIe on a wide variety of CM4IO-compatible boards which use the nEXTRST signal. Fixes:5859b5a9c3("arm64: dts: rockchip: add SoQuartz CM4IO dts") Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20230421152610.21688-1-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
193 lines
3.6 KiB
Plaintext
193 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include "rk3566-soquartz.dtsi"
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/ {
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model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
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compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
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/* labeled +12v in schematic */
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vcc12v_dcin: vcc12v-dcin-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc12v_dcin";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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/* labeled +5v in schematic */
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vcc_5v: vcc-5v-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_5v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc12v_dcin>;
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};
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vcc_sd_pwr: vcc-sd-pwr-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_sd_pwr";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc3v3_sys>;
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};
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};
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/* phy for pcie */
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&combphy2 {
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phy-supply = <&vcc3v3_sys>;
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status = "okay";
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};
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&gmac1 {
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status = "okay";
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};
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/*
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* i2c1 is exposed on CM1 / Module1A
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* pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
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* pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
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*/
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&i2c1 {
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status = "okay";
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/*
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* the rtc interrupt is tied to PMIC_PWRON,
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* it will force reset the board if triggered.
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*/
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pcf85063: rtc@51 {
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compatible = "nxp,pcf85063";
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reg = <0x51>;
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};
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};
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/*
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* i2c2 is exposed on CM1 / Module1A - to PI40
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* pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
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* pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
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*/
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&i2c2 {
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status = "disabled";
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};
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/*
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* i2c3 is exposed on CM1 / Module1A - to PI40
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* pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
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* pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
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*/
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&i2c3 {
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status = "disabled";
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};
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/*
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* i2c4 is exposed on CM2 / Module1B - to PI40
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* pin 45 - GPIO24 - i2c4_scl_m1
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* pin 47 - GPIO23 - i2c4_sda_m1
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*/
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&i2c4 {
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status = "disabled";
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};
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/*
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* i2s1_8ch is exposed on CM1 / Module1A - to PI40
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* pin 24 - GPIO26 - i2s1_sdi1_m1
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* pin 25 - GPIO21 - i2s1_sdo0_m1
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* pin 26 - GPIO19 - i2s1_lrck_tx_m1
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* pin 27 - GPIO20 - i2s1_sdi0_m1
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* pin 29 - GPIO16 - i2s1_sdi3_m1
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* pin 30 - GPIO6 - i2s1_sdi2_m1
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* pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
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* pin 41 - GPIO25 - i2s1_sdo2_m1
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* pin 49 - GPIO18 - i2s1_sclk_tx_m1
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* pin 50 - GPIO17 - i2s1_mclk_m1
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* pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
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*/
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&i2s1_8ch {
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status = "disabled";
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};
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&led_diy {
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status = "okay";
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};
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&led_work {
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status = "okay";
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};
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&pcie2x1 {
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vpcie3v3-supply = <&vcc_3v3>;
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status = "okay";
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};
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&rgmii_phy1 {
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status = "okay";
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};
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/*
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* saradc is exposed on CM1 / Module1A - to J2
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* pin 94 - AIN1 - saradc_vin3
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* pin 96 - AIN0 - saradc_vin2
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*/
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&saradc {
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status = "disabled";
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};
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&sdmmc0 {
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vmmc-supply = <&vcc_sd_pwr>;
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status = "okay";
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};
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/*
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* spi3 is exposed on CM1 / Module1A - to PI40
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* pin 37 - GPIO7 - spi3_cs1_m0
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* pin 38 - GPIO11 - spi3_clk_m0
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* pin 39 - GPIO8 - spi3_cs0_m0
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* pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
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* pin 44 - GPIO10 - spi3_mosi_m0
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*/
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&spi3 {
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status = "disabled";
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};
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/*
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* uart2 is exposed on CM1 / Module1A - to PI40
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* pin 51 - GPIO15 - uart2_rx_m0
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* pin 55 - GPIO14 - uart2_tx_m0
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*/
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&uart2 {
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status = "okay";
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};
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/*
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* uart7 is exposed on CM1 / Module1A - to PI40
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* pin 46 - GPIO22 - uart7_tx_m2
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* pin 47 - GPIO23 - uart7_rx_m2
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*/
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&uart7 {
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status = "okay";
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};
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&usb2phy0 {
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status = "okay";
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};
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&usb2phy0_otg {
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phy-supply = <&vcc_5v>;
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status = "okay";
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};
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&usb_host0_xhci {
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status = "okay";
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};
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&vbus {
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vin-supply = <&vcc_5v>;
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};
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