5ee52118ac
Expose the device state through an attribute in sysfs and allow to change it. This is to stop and shutdown a QAT device in order to change its configuration. The state attribute has been added to a newly created `qat` attribute group which will contain all _QAT specific_ attributes. The logic that implements the sysfs entries is part of a new file, adf_sysfs.c. This exposes an entry point to allow the driver to create attributes. The function that creates the sysfs attributes is called from the probe function of the driver and not in the state machine init function to allow the change of states even if the device is in the down state. In order to restore the device configuration between a transition from down to up, the function that configures the devices has been abstracted into the HW data structure. The `state` attribute is only exposed for qat_4xxx devices. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Co-developed-by: Tomasz Kowallik <tomaszx.kowalik@intel.com> Signed-off-by: Tomasz Kowallik <tomaszx.kowalik@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Vladis Dronov <vdronov@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef ADF_4XXX_HW_DATA_H_
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#define ADF_4XXX_HW_DATA_H_
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#include <adf_accel_devices.h>
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/* PCIe configuration space */
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#define ADF_4XXX_SRAM_BAR 0
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#define ADF_4XXX_PMISC_BAR 1
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#define ADF_4XXX_ETR_BAR 2
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#define ADF_4XXX_RX_RINGS_OFFSET 1
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#define ADF_4XXX_TX_RINGS_MASK 0x1
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#define ADF_4XXX_MAX_ACCELERATORS 1
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#define ADF_4XXX_MAX_ACCELENGINES 9
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#define ADF_4XXX_BAR_MASK (BIT(0) | BIT(2) | BIT(4))
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/* Physical function fuses */
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#define ADF_4XXX_FUSECTL0_OFFSET (0x2C8)
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#define ADF_4XXX_FUSECTL1_OFFSET (0x2CC)
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#define ADF_4XXX_FUSECTL2_OFFSET (0x2D0)
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#define ADF_4XXX_FUSECTL3_OFFSET (0x2D4)
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#define ADF_4XXX_FUSECTL4_OFFSET (0x2D8)
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#define ADF_4XXX_FUSECTL5_OFFSET (0x2DC)
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#define ADF_4XXX_ACCELERATORS_MASK (0x1)
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#define ADF_4XXX_ACCELENGINES_MASK (0x1FF)
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#define ADF_4XXX_ADMIN_AE_MASK (0x100)
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#define ADF_4XXX_ETR_MAX_BANKS 64
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/* MSIX interrupt */
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#define ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET (0x41A040)
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#define ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET (0x41A044)
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#define ADF_4XXX_SMIAPF_MASK_OFFSET (0x41A084)
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#define ADF_4XXX_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i) * 0x04))
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/* Bank and ring configuration */
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#define ADF_4XXX_NUM_RINGS_PER_BANK 2
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#define ADF_4XXX_NUM_BANKS_PER_VF 4
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/* Arbiter configuration */
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#define ADF_4XXX_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
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#define ADF_4XXX_ARB_OFFSET (0x0)
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#define ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET (0x400)
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/* Admin Interface Reg Offset */
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#define ADF_4XXX_ADMINMSGUR_OFFSET (0x500574)
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#define ADF_4XXX_ADMINMSGLR_OFFSET (0x500578)
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#define ADF_4XXX_MAILBOX_BASE_OFFSET (0x600970)
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/* Firmware Binaries */
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#define ADF_4XXX_FW "qat_4xxx.bin"
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#define ADF_4XXX_MMP "qat_4xxx_mmp.bin"
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#define ADF_4XXX_SYM_OBJ "qat_4xxx_sym.bin"
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#define ADF_4XXX_DC_OBJ "qat_4xxx_dc.bin"
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#define ADF_4XXX_ASYM_OBJ "qat_4xxx_asym.bin"
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#define ADF_4XXX_ADMIN_OBJ "qat_4xxx_admin.bin"
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/* qat_4xxx fuse bits are different from old GENs, redefine them */
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enum icp_qat_4xxx_slice_mask {
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ICP_ACCEL_4XXX_MASK_CIPHER_SLICE = BIT(0),
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ICP_ACCEL_4XXX_MASK_AUTH_SLICE = BIT(1),
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ICP_ACCEL_4XXX_MASK_PKE_SLICE = BIT(2),
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ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3),
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ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4),
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ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5),
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ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6),
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};
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void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data);
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void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data);
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int adf_crypto_dev_config(struct adf_accel_dev *accel_dev);
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#endif
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