a73b31a8da
Compared with RK3288/RK3399, the HBR2 link rate support is the main improvement of RK3588 eDP TX controller, and there are also two independent eDP display interfaces on RK3588 Soc. The newly added 'apb' reset is to ensure the APB bus of eDP controller works well on the RK3588 SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Change-Id: If3864613762898624ba39ad0395516a4ebb02732 Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Link: https://lore.kernel.org/r/20250310104114.2608063-10-damon.ding@rock-chips.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> (cherry picked from commit f855146263b14abadd8d5bd0e280e54fbab3bd18)
122 lines
2.4 KiB
YAML
122 lines
2.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip specific extensions to the Analogix Display Port
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maintainers:
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- Sandy Huang <hjc@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,rk3288-dp
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- rockchip,rk3399-edp
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- rockchip,rk3588-edp
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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items:
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- const: dp
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- const: pclk
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- const: grf
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power-domains:
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maxItems: 1
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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items:
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- const: dp
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- const: apb
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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This SoC makes use of GRF regs.
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required:
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- compatible
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- clocks
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- clock-names
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- resets
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- reset-names
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- rockchip,grf
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allOf:
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- $ref: /schemas/display/bridge/analogix,dp.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,rk3588-edp
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then:
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properties:
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resets:
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minItems: 2
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reset-names:
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minItems: 2
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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dp@ff970000 {
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compatible = "rockchip,rk3288-dp";
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reg = <0xff970000 0x4000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
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clock-names = "dp", "pclk";
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phys = <&dp_phy>;
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phy-names = "dp";
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resets = <&cru 111>;
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reset-names = "dp";
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rockchip,grf = <&grf>;
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pinctrl-0 = <&edp_hpd>;
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pinctrl-names = "default";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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edp_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_edp>;
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};
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edp_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_edp>;
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};
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};
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edp_out: port@1 {
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reg = <1>;
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edp_out_panel: endpoint {
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remote-endpoint = <&panel_in_edp>;
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};
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};
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};
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};
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