Signed-off-by: Su Yuefu <yuefu.su@rock-chips.com> Change-Id: I090f11d77d4355d7b1ccf7e098770eab699f2f89
285 lines
4.5 KiB
Plaintext
285 lines
4.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*
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*/
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/*
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* csi2_dphy0 -> csi0(rx0) clk0 + 4 lane
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* csi2_dphy1 -> csi0(rx0) clk0 + 2 lane 0/1
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* csi2_dphy2 -> csi0(rx0) clk1 + 2 lane 2/3
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* csi2_dphy3 -> csi1(rx1) clk0 + 4 lane
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* csi2_dphy4 -> csi1(rx1) clk0 + 2 lane 0/1
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* csi2_dphy5 -> csi1(rx1) clk1 + 2 lane 2/3
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*/
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&csi2_dphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy_input0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&sc450ai_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi0_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy3 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy3_input0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&sc450ai_1_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy3_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi2_csi2_input>;
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-0 = <&i2c1m2_pins>;
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sc450ai: sc450ai@30 {
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compatible = "smartsens,sc450ai";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru CLK_MIPI0_OUT2IO>;
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clock-names = "xvclk";
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reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clk0_pins>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "default";
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rockchip,camera-module-lens-name = "default";
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port {
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sc450ai_out: endpoint {
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remote-endpoint = <&csi_dphy_input0>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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sc450ai_1: sc450ai-1@32 {
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compatible = "smartsens,sc450ai";
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status = "okay";
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reg = <0x32>;
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clocks = <&cru CLK_MIPI1_OUT2IO>;
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clock-names = "xvclk";
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reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio6 RK_PA0 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clk1_pins>;
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rockchip,camera-module-index = <1>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "default";
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rockchip,camera-module-lens-name = "default";
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port {
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sc450ai_1_out: endpoint {
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remote-endpoint = <&csi_dphy3_input0>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&mipi0_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy0_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in0>;
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};
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};
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};
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};
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&mipi2_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy3_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in2>;
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};
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};
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};
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};
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&rkcif {
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status = "okay";
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};
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&rkcif_mipi_lvds {
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status = "okay";
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port {
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cif_mipi_in0: endpoint {
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remote-endpoint = <&mipi0_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds_sditf {
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status = "okay";
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port {
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mipi_lvds_sditf: endpoint {
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remote-endpoint = <&isp_vir0>;
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};
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};
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};
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&rkcif_mipi_lvds2 {
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status = "okay";
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port {
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cif_mipi_in2: endpoint {
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remote-endpoint = <&mipi2_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds2_sditf {
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status = "okay";
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port {
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mipi_lvds2_sditf: endpoint {
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remote-endpoint = <&isp_vir1>;
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};
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};
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};
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&rkcif_mmu {
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status = "okay";
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};
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&rkisp {
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status = "okay";
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};
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&rkisp_mmu {
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status = "okay";
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};
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&rkisp_vir0 {
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status = "okay";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp_vir0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_lvds_sditf>;
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};
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};
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};
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&rkisp_vir0_sditf {
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status = "okay";
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};
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&rkisp_vir1 {
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status = "okay";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp_vir1: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_lvds2_sditf>;
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};
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};
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};
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&rkisp_vir1_sditf {
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status = "okay";
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};
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&rkvpss_vir0 {
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status = "okay";
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};
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&rkvpss_vir1 {
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status = "okay";
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}; |