52f8f5cff0
1.add the function of configure ddr timing such us sr_idle, pd_idle, odt
disable frequency, dll bypass frequency, odt strength, driver strength in dts.
2.make sure commit 8be554a502 ("rk3368 dts: add ddr timing node in
rk3368.dtsi" add ddr timing node in dts that user can configure ddr timing in
dts file.) was merged.
3.bl30 must update to rk3368bl30_v2.11.bin.
Change-Id: Ie8ae559c8128eb01788271a4333c465e21954ab1
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/*
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* SCPI Message Protocol driver header
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*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/types.h>
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#include <linux/rockchip/common.h>
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struct scpi_opp_entry {
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u32 freq_hz;
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u32 volt_mv;
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} __packed;
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struct scpi_opp {
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struct scpi_opp_entry *opp;
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u32 latency; /* in usecs */
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int count;
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} __packed;
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unsigned long scpi_clk_get_val(u16 clk_id);
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int scpi_clk_set_val(u16 clk_id, unsigned long rate);
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int scpi_dvfs_get_idx(u8 domain);
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int scpi_dvfs_set_idx(u8 domain, u8 idx);
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struct scpi_opp *scpi_dvfs_get_opps(u8 domain);
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int scpi_get_sensor(char *name);
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int scpi_get_sensor_value(u16 sensor, u32 *val);
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int scpi_sys_set_mcu_state_suspend(void);
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int scpi_sys_set_mcu_state_resume(void);
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int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type,
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u32 addr_mcu_el3);
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int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
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int scpi_ddr_send_timing(u32 *p, u32 size);
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int scpi_ddr_round_rate(u32 m_hz);
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int scpi_ddr_set_auto_self_refresh(u32 en);
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int scpi_ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
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struct ddr_bw_info *ddr_bw_ch1);
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int scpi_ddr_get_clk_rate(void);
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int scpi_thermal_get_temperature(void);
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int scpi_thermal_set_clk_cycle(u32 cycle);
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