25fdd5933e
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
[robclark minor rebase]
Signed-off-by: Rob Clark <robdclark@gmail.com>
137 lines
4.5 KiB
C
137 lines
4.5 KiB
C
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DPU_FORMATS_H
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#define _DPU_FORMATS_H
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#include <drm/drm_fourcc.h>
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#include "msm_gem.h"
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#include "dpu_hw_mdss.h"
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/**
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* dpu_get_dpu_format_ext() - Returns dpu format structure pointer.
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* @format: DRM FourCC Code
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* @modifiers: format modifier array from client, one per plane
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*/
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const struct dpu_format *dpu_get_dpu_format_ext(
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const uint32_t format,
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const uint64_t modifier);
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#define dpu_get_dpu_format(f) dpu_get_dpu_format_ext(f, 0)
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/**
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* dpu_get_msm_format - get an dpu_format by its msm_format base
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* callback function registers with the msm_kms layer
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* @kms: kms driver
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* @format: DRM FourCC Code
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* @modifiers: data layout modifier
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*/
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const struct msm_format *dpu_get_msm_format(
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struct msm_kms *kms,
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const uint32_t format,
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const uint64_t modifiers);
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/**
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* dpu_populate_formats - populate the given array with fourcc codes supported
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* @format_list: pointer to list of possible formats
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* @pixel_formats: array to populate with fourcc codes
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* @pixel_modifiers: array to populate with drm modifiers, can be NULL
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* @pixel_formats_max: length of pixel formats array
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* Return: number of elements populated
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*/
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uint32_t dpu_populate_formats(
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const struct dpu_format_extended *format_list,
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uint32_t *pixel_formats,
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uint64_t *pixel_modifiers,
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uint32_t pixel_formats_max);
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/**
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* dpu_format_get_plane_sizes - calculate size and layout of given buffer format
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* @fmt: pointer to dpu_format
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* @w: width of the buffer
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* @h: height of the buffer
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* @layout: layout of the buffer
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* @pitches: array of size [DPU_MAX_PLANES] to populate
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* pitch for each plane
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*
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* Return: size of the buffer
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*/
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int dpu_format_get_plane_sizes(
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const struct dpu_format *fmt,
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const uint32_t w,
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const uint32_t h,
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struct dpu_hw_fmt_layout *layout,
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const uint32_t *pitches);
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/**
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* dpu_format_get_block_size - get block size of given format when
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* operating in block mode
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* @fmt: pointer to dpu_format
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* @w: pointer to width of the block
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* @h: pointer to height of the block
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*
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* Return: 0 if success; error oode otherwise
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*/
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int dpu_format_get_block_size(const struct dpu_format *fmt,
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uint32_t *w, uint32_t *h);
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/**
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* dpu_format_check_modified_format - validate format and buffers for
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* dpu non-standard, i.e. modified format
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* @kms: kms driver
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* @msm_fmt: pointer to the msm_fmt base pointer of an dpu_format
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* @cmd: fb_cmd2 structure user request
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* @bos: gem buffer object list
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*
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* Return: error code on failure, 0 on success
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*/
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int dpu_format_check_modified_format(
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const struct msm_kms *kms,
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const struct msm_format *msm_fmt,
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const struct drm_mode_fb_cmd2 *cmd,
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struct drm_gem_object **bos);
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/**
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* dpu_format_populate_layout - populate the given format layout based on
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* mmu, fb, and format found in the fb
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* @aspace: address space pointer
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* @fb: framebuffer pointer
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* @fmtl: format layout structure to populate
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*
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* Return: error code on failure, -EAGAIN if success but the addresses
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* are the same as before or 0 if new addresses were populated
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*/
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int dpu_format_populate_layout(
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struct msm_gem_address_space *aspace,
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struct drm_framebuffer *fb,
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struct dpu_hw_fmt_layout *fmtl);
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/**
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* dpu_format_get_framebuffer_size - get framebuffer memory size
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* @format: DRM pixel format
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* @width: pixel width
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* @height: pixel height
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* @pitches: array of size [DPU_MAX_PLANES] to populate
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* pitch for each plane
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* @modifiers: drm modifier
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*
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* Return: memory size required for frame buffer
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*/
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uint32_t dpu_format_get_framebuffer_size(
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const uint32_t format,
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const uint32_t width,
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const uint32_t height,
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const uint32_t *pitches,
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const uint64_t modifiers);
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#endif /*_DPU_FORMATS_H */
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