Files
rockchip-kernel/arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi
William Wu 2495fa0c05 arm64: dts: rockchip: fix usb nodes for rk356x boards
This patch adds phy property for usb on various rk356x boards.
3566 EVB1 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST + 2 x USB2.0 HOST
3566 EVB2 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST + 2 x USB2.0 HOST
3566 EVB3 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST(mux with SATA, default for SATA) + 2 x USB2.0 HOST
3568 EVB1 1 x USB3.0 OTG(Type-A USB3.0 + Micro USB2.0)+ 1 x USB3.0 HOST + 2 x USB2.0 HOST
3568 EVB6 1 x USB3.0 OTG(Type-A USB3.0 + Micro USB2.0)+ 3 x USB2.0 HOST

Change-Id: If1e2cdb03e50e770337648f59f0375034b7062cd
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-19 20:50:25 +08:00

275 lines
5.0 KiB
Plaintext

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3568-evb.dtsi"
/ {
model = "Rockchip RK3566 EVB1 DDR4 V10 Board";
compatible = "rockchip,rk3566-evb1-ddr4-v10", "rockchip,rk3568";
pcie20_3v3: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "pcie20_3v3";
regulator-min-microvolt = <0100000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
gpios-states = <0x1>;
states = <0100000 0x0
3300000 0x1>;
};
rk_headset: rk-headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
};
};
&audiopwmout_diff {
status = "disabled";
};
&combphy1_usq {
status = "okay";
};
&combphy2_psq {
status = "disabled";
};
&dig_acodec {
status = "disabled";
rockchip,pwm-output-mode;
pinctrl-names = "default";
pinctrl-0 = <&audiopwmoutdiff_pins>;
};
/*
* mipi_dphy0 needs to be enabled
* when dsi0 is enabled
*/
&dsi0 {
status = "okay";
};
&dsi0_in_vp0 {
status = "okay";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi0_panel {
power-supply = <&vcc3v3_lcd0_n>;
reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd0_rst_gpio>;
};
/*
* mipi_dphy1 needs to be enabled
* when dsi1 is enabled
*/
&dsi1 {
status = "disabled";
};
&dsi1_in_vp0 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&dsi1_panel {
power-supply = <&vcc3v3_lcd1_n>;
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd1_rst_gpio>;
};
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
&gt1x {
power-supply = <&vcc3v3_lcd0_n>;
};
&sdio_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
};
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim_pins &gmac0_rgmii_pins>;
tx_delay = <0x38>;
rx_delay = <0x2c>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&i2s3_2ch {
status = "disabled";
rockchip,clk-trcm = <2>;
};
&mdio0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
&mipi_dphy0 {
status = "okay";
};
&mipi_dphy1 {
status = "disabled";
};
&pcie2x1 {
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&pcie20_3v3>;
status = "disabled";
};
&pdm {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&pdmclk1m1
&pdmsdi1m1
&pdmsdi2m1
&pdmsdi3m1>;
};
&pdmics {
status = "disabled";
};
&pdm_mic_array {
status = "disabled";
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1m1_xfer &uart1ctsnm1>;
};
&usbdrd_dwc3 {
dr_mode = "otg";
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
extcon = <&usb2phy0>;
maximum-speed = "high-speed";
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&wireless_wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
wifi_chip_type = "ap6398s";
WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&wireless_bluetooth {
compatible = "bluetooth-platdata";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart1rtsnm1>;
pinctrl-1 = <&uart1_gpios>;
BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pinctrl {
headphone {
hp_det: hp-det {
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
lcd0 {
lcd0_rst_gpio: lcd0-rst-gpio {
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd1 {
lcd1_rst_gpio: lcd1-rst-gpio {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {
uart1_gpios: uart1-gpios {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};