ab883313ef
Allwinner H3 SoC also contains MBUS controller. Add compatible for it. Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
Allwinner Memory Bus (MBUS) controller
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The MBUS controller drives the MBUS that other devices in the SoC will
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use to perform DMA. It also has a register interface that allows to
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monitor and control the bandwidth and priorities for masters on that
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bus.
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Required properties:
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- compatible: Must be one of:
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- allwinner,sun5i-a13-mbus
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- allwinner,sun8i-h3-mbus
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- reg: Offset and length of the register set for the controller
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- clocks: phandle to the clock driving the controller
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- dma-ranges: See section 2.3.9 of the DeviceTree Specification
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- #interconnect-cells: Must be one, with the argument being the MBUS
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port ID
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Each device having to perform their DMA through the MBUS must have the
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interconnects and interconnect-names properties set to the MBUS
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controller and with "dma-mem" as the interconnect name.
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Example:
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mbus: dram-controller@1c01000 {
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compatible = "allwinner,sun5i-a13-mbus";
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reg = <0x01c01000 0x1000>;
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clocks = <&ccu CLK_MBUS>;
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dma-ranges = <0x00000000 0x40000000 0x20000000>;
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#interconnect-cells = <1>;
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};
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fe0: display-frontend@1e00000 {
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compatible = "allwinner,sun5i-a13-display-frontend";
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...
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interconnects = <&mbus 19>;
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interconnect-names = "dma-mem";
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};
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