This patch to generate the rk3568-pinctrl.dtsi again by pin2dts tool
which has been updated with some bugs fixed, such as lack of comment
for some nodes.
Now the pin2dts can generate the auto part of pinctrl file absolutely,
changes including:
* file header
/SPDX-License head
/#include <something>
&pinctrl {
};
* full rules
make the auto part can be generated by rules without any handly modify
special case: pwm4 which may be matched as pw-m4, that means the module
is pw and its mux mode is m4.
Change-Id: Ia92668ab938c1c05dfe430cf67b6f73bafaa31c3
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
282 lines
5.1 KiB
Plaintext
282 lines
5.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3568-evb.dtsi"
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/ {
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model = "Rockchip RK3566 EVB1 DDR4 V10 Board";
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compatible = "rockchip,rk3566-evb1-ddr4-v10", "rockchip,rk3568";
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pcie20_3v3: gpio-regulator {
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compatible = "regulator-gpio";
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regulator-name = "pcie20_3v3";
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regulator-min-microvolt = <0100000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
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gpios-states = <0x1>;
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states = <0100000 0x0
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3300000 0x1>;
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};
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rk_headset: rk-headset {
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compatible = "rockchip_headset";
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headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&hp_det>;
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};
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};
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&audiopwmout_diff {
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status = "disabled";
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};
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&combphy1_usq {
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status = "okay";
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};
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&combphy2_psq {
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status = "disabled";
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};
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&dig_acodec {
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status = "disabled";
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rockchip,pwm-output-mode;
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pinctrl-names = "default";
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pinctrl-0 = <&audiopwm_loutp
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&audiopwm_loutn
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&audiopwm_routp
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&audiopwm_routn
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>;
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};
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/*
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* mipi_dphy0 needs to be enabled
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* when dsi0 is enabled
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*/
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&dsi0 {
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status = "okay";
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};
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&dsi0_in_vp0 {
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status = "okay";
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};
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&dsi0_in_vp1 {
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status = "disabled";
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};
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&dsi0_panel {
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power-supply = <&vcc3v3_lcd0_n>;
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reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcd0_rst_gpio>;
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};
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/*
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* mipi_dphy1 needs to be enabled
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* when dsi1 is enabled
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*/
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&dsi1 {
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status = "disabled";
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};
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&dsi1_in_vp0 {
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status = "disabled";
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};
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&dsi1_in_vp1 {
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status = "disabled";
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};
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&dsi1_panel {
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power-supply = <&vcc3v3_lcd1_n>;
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reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcd1_rst_gpio>;
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};
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/*
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* power-supply should switche to vcc3v3_lcd1_n
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* when mipi panel is connected to dsi1.
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*/
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>1x {
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power-supply = <&vcc3v3_lcd0_n>;
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};
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&sdio_pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&rk809 1>;
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clock-names = "ext_clock";
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_enable_h>;
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/*
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* On the module itself this is one of these (depending
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* on the actual card populated):
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* - SDIO_RESET_L_WL_REG_ON
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* - PDN (power down when low)
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*/
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reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
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};
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&gmac0 {
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phy-mode = "rgmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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tx_delay = <0x38>;
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rx_delay = <0x2c>;
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phy-handle = <&rgmii_phy0>;
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status = "okay";
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};
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&i2s3_2ch {
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status = "disabled";
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};
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&mdio0 {
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rgmii_phy0: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&mipi_dphy0 {
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status = "okay";
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};
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&mipi_dphy1 {
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status = "disabled";
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};
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&pcie2x1 {
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reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&pcie20_3v3>;
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status = "disabled";
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};
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&pdm {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&pdmm1_clk1
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&pdmm1_sdi1
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&pdmm1_sdi2
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&pdmm1_sdi3>;
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};
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&pdmics {
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status = "disabled";
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};
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&pdm_mic_array {
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status = "disabled";
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>;
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};
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&usbdrd_dwc3 {
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dr_mode = "otg";
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phys = <&u2phy0_otg>;
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phy-names = "usb2-phy";
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extcon = <&usb2phy0>;
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maximum-speed = "high-speed";
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status = "okay";
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};
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&usbdrd30 {
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status = "okay";
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};
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&vcc3v3_lcd0_n {
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gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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&vcc3v3_lcd1_n {
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gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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&wireless_wlan {
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compatible = "wlan-platdata";
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rockchip,grf = <&grf>;
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_host_wake_irq>;
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wifi_chip_type = "ap6398s";
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WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&wireless_bluetooth {
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compatible = "bluetooth-platdata";
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clocks = <&rk809 1>;
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clock-names = "ext_clock";
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//wifi-bt-power-toggle;
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uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default", "rts_gpio";
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pinctrl-0 = <&uart1m1_rtsn>;
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pinctrl-1 = <&uart1_gpios>;
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BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
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BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&pinctrl {
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headphone {
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hp_det: hp-det {
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rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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lcd0 {
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lcd0_rst_gpio: lcd0-rst-gpio {
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rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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lcd1 {
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lcd1_rst_gpio: lcd1-rst-gpio {
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rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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wireless-wlan {
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wifi_host_wake_irq: wifi-host-wake-irq {
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rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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wireless-bluetooth {
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uart1_gpios: uart1-gpios {
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rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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