18864e8b83
commita06ed27f3bupstream. Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Cc: stable@vger.kernel.org # 5.10+ Fixes:2d87061e70("arm64: dts: ti: Add Support for J721E SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-3-nm@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
186 lines
5.9 KiB
Plaintext
186 lines
5.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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/ {
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model = "Texas Instruments K3 J721E SoC";
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compatible = "ti,j721e";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &wkup_uart0;
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serial1 = &mcu_uart0;
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serial2 = &main_uart0;
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serial3 = &main_uart1;
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serial4 = &main_uart2;
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serial5 = &main_uart3;
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serial6 = &main_uart4;
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serial7 = &main_uart5;
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serial8 = &main_uart6;
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serial9 = &main_uart7;
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serial10 = &main_uart8;
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serial11 = &main_uart9;
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ethernet0 = &cpsw_port1;
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};
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chosen { };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a72";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a72";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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next-level-cache = <&msmc_l3>;
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};
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msmc_l3: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a72_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,armv8-pmuv3";
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/* Recommendation from GIC500 TRM Table A.3 */
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: bus@100000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
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<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
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<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
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<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
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<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
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<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
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<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
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<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
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<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
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<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
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<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
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<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
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<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
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<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
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<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
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<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
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<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
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<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
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/* MCUSS_WKUP Range */
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
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<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
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cbass_mcu_wakeup: bus@28380000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
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<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
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<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
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<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
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<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
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<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
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<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
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<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
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<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
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};
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};
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};
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/* Now include the peripherals for each bus segments */
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#include "k3-j721e-main.dtsi"
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#include "k3-j721e-mcu-wakeup.dtsi"
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