Files
rockchip-kernel/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts
Guochun Huang 1f429c9dc1 dt-bindings: display: drm_mipi_dsi: Add _NO_ to MIPI_DSI_* flags disabling features
As described in:

commit 0f3b68b66a ("drm/dsi: Add _NO_ to MIPI_DSI_* flags disabling features")

Many of the DSI flags have names opposite to their actual effects,
e.g. MIPI_DSI_MODE_EOT_PACKET means that EoT packets will actually
be disabled. Fix this by including _NO_ in the flag names, e.g.
MIPI_DSI_MODE_NO_EOT_PACKET.

Change-Id: Ibf5faf52f95a1ab07c3ffb7848ff1be7071c458b
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
2024-07-11 16:22:56 +08:00

138 lines
2.4 KiB
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/rockchip_vop.h>
#include "rk3568m-serdes-evb-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"
&i2c1 {
status = "okay";
clock-frequency = <10000>;
};
&dsi0 {
status = "okay";
};
&dsi0_in_vp0 {
status = "okay";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi0_panel {
status = "okay";
dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET |
MIPI_DSI_CLOCK_NON_CONTINUOUS)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [];
panel-exit-sequence = [];
};
&dsi0_timing0 {
clock-frequency = <50000000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <160>;
hsync-len = <20>;
hback-porch = <140>;
vfront-porch = <12>;
vsync-len = <3>;
vback-porch = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
&video_phy0 {
status = "okay";
};
&rgb {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
rgb_out_rkx110_x120: endpoint {
remote-endpoint = <&rkx110_x120_in_rgb>;
};
};
};
};
&rgb_in_vp2 {
status = "okay";
};
&rkx110_reset_gpio {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
&rkx110_x120 {
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&rkx110_reset_gpio>;
};
&serdes_timing0 {
clock-frequency = <50000000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <160>;
hsync-len = <20>;
hback-porch = <140>;
vfront-porch = <12>;
vsync-len = <3>;
vback-porch = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
&serdes_panel {
dsi-rx,lanes = <4>;
//dsi-rx,video-mode;
local-port0 = <RK_SERDES_DSI_RX1>;
remote0-port0 = <RK_SERDES_RGB_TX>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
rkx110_x120_in_rgb: endpoint {
remote-endpoint = <&rgb_out_rkx110_x120>;
};
};
};
};
/* vp0 for HDMI, vp2 for rgb */
&vp0 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 |
1 << ROCKCHIP_VOP2_SMART0)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
};
&vp2 {
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 |
1 << ROCKCHIP_VOP2_SMART1)>;
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
};