Update all 64bit rockchip devicetree files to use SPDX-License-Identifiers.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ie983cca0d54cae8b5ad6d322d51eb7bbd265aa0a
As a second global reset, the GRF is not reset, the iomux and
pull of PWM pin is still keeping, but PWM controller is reset,
PWM pin goes into input mode. However, the pull is still none
changed in kernel, which can cause voltage problems, so should
always keep the PWM pin pull down mode, with 0~50 μA power
increase.
Change-Id: Ibb1cbb5f5371d7838783264e23d5160c0757aaa6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Fusb302 driver uses gpiod_set_value() to control VBUS, so vbus-5v-gpios
flags should be used correctly in device tree.
Change-Id: Ie7f0d1d290750bbf4207c1bc5665e4a0427a7a97
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
The vcc_sd is used for IO voltage for sdmmc interface on rk3399
platform have a limitation that it can't be larger than 3.0v, otherwise
it has a potential risk for the chip. Correct all of them.
Change-Id: I8d4ee2202fb32d30734c98a3b514c315e62859b4
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
invert the pwm polarity for new pwm interface
Change-Id: I8dfde14fbc4fd4aa907722f260ce72fdb4d7d3bb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add a new dtsi file - rk3399-opp.dtsi, to configure opp-tables
for cpu, gpu and dmc.
Add rk3399-early-opp.dtsi for board with ES1, which need limit
frequency for cpu, gpu and dmc.
Change-Id: Ib57761fd5f405b0e79039d7a01e6e023d6f5dc2c
Reviewed-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Huang, Tao <huangtao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
We may miss clock-latency-ns when disable some opps, then cpufreq
will fallback to performance governor, so add clock-latency-ns for
each opp to make disable opp easy.
code as below:
drivers/cpufreq/cpufreq.c:2010
if (policy->governor->max_transition_latency &&
policy->cpuinfo.transition_latency >
policy->governor->max_transition_latency) {
if (!gov)
return -EINVAL;
else {
pr_warn("%s governor failed, too long transition latency of HW,
fallback to %s governor\n",
policy->governor->name, gov->name);
policy->governor = gov;
}
}
Change-Id: I93cff667deb487baa0115b7af0206f0803010d37
Signed-off-by: Chen Liang <cl@rock-chips.com>
margin 25mV-50mV, stress test:
1. antutu-3d, use governor simpleondemand
2. webgl, fish number 50, sweep frequency
3. glmark2, run texture and shadow, sweep frequency
Change-Id: Ia2682610e948df7df2ad190ac3a28b2dad464cb3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
used to calculate the delay time for change dcdc voltage.
Change-Id: I6bb462ef087b9ce6aa98991a1b961ed5f57bb3c8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The opp table can cover the chips whose leakage is between 30mA and 60mA.
Change-Id: I50be3923eb6016cba6309380006ce902d22fe123
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Set vsel pin to active to disable DCDC,
Set vsel pin to inactive to enable DCDC.
Change-Id: Ie7d98730e5f59ffe38f0b88388cfb5b852316fe3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RK3399 EVB1 and EVB2 use pwm3 for vdd_center, but EVB3 use pwm2.
This patch moved the vdd_center node to each board dtsi file.
Change-Id: I2b46b06b622c30ab65f26663a3628e73733472ad
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Some evb3 need 1v for 800M.
We remove 700M currently since havn't a good opinion of it.
Change-Id: I7083857f5bb8a09efe0369a6bdd49e28c67da8b7
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add to support RK3399 evb reversion 3, with ES2.
Change-Id: Ia07a19d600a6acc1e503e9e56c78d2f60f4ef9be
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
