Update all 64bit rockchip devicetree files to use SPDX-License-Identifiers.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ie983cca0d54cae8b5ad6d322d51eb7bbd265aa0a
Fusb302 driver uses gpiod_set_value() to control VBUS, so vbus-5v-gpios
flags should be used correctly in device tree.
Change-Id: Ie7f0d1d290750bbf4207c1bc5665e4a0427a7a97
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
As a second global reset, the GRF is not reset, the iomux and
pull of PWM pin is still keeping, but PWM controller is reset,
PWM pin goes into input mode. However, the pull is still none
changed in kernel, which can cause voltage problems, so should
always keep the PWM pin pull down mode, with 0~50 μA power
increase.
Change-Id: Ibbb9465f7c550d49d416bc3438c5199434df6eba
Signed-off-by: David Wu <david.wu@rock-chips.com>
The vcc_sd is used for IO voltage for sdmmc interface on rk3399
platform have a limitation that it can't be larger than 3.0v, otherwise
it has a potential risk for the chip. Correct all of them.
Change-Id: I8d4ee2202fb32d30734c98a3b514c315e62859b4
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
invert the pwm polarity for new pwm interface
Change-Id: I8dfde14fbc4fd4aa907722f260ce72fdb4d7d3bb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add a new dtsi file - rk3399-opp.dtsi, to configure opp-tables
for cpu, gpu and dmc.
Add rk3399-early-opp.dtsi for board with ES1, which need limit
frequency for cpu, gpu and dmc.
Change-Id: Ib57761fd5f405b0e79039d7a01e6e023d6f5dc2c
Reviewed-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Huang, Tao <huangtao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
We may miss clock-latency-ns when disable some opps, then cpufreq
will fallback to performance governor, so add clock-latency-ns for
each opp to make disable opp easy.
code as below:
drivers/cpufreq/cpufreq.c:2010
if (policy->governor->max_transition_latency &&
policy->cpuinfo.transition_latency >
policy->governor->max_transition_latency) {
if (!gov)
return -EINVAL;
else {
pr_warn("%s governor failed, too long transition latency of HW,
fallback to %s governor\n",
policy->governor->name, gov->name);
policy->governor = gov;
}
}
Change-Id: I93cff667deb487baa0115b7af0206f0803010d37
Signed-off-by: Chen Liang <cl@rock-chips.com>
used to calculate the delay time for change dcdc voltage.
Change-Id: I6bb462ef087b9ce6aa98991a1b961ed5f57bb3c8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Since evb2 couple with ES1, the power consumption is large enough to
shutdown device in some case.
Let's reduce it's support lists to make things simple.
Change-Id: I145aa0c6a21e41b3c8e6ff32fd15839baa15f81e
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
RK3399 EVB1 and EVB2 use pwm3 for vdd_center, but EVB3 use pwm2.
This patch moved the vdd_center node to each board dtsi file.
Change-Id: I2b46b06b622c30ab65f26663a3628e73733472ad
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The usb2 phy utmi bvalid status is invalid for ES1 evb1/evb2
board, so check vbus status by utmi avalid status.
Change-Id: Iae369183cd15034eb35818c63988150f3aad6374
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Big cores' power consumption and gpu's are greatly reduced, ipa parameters
are ajusted accordingly.
Change-Id: Ibfdae1856c2f1c2cf80a0a2f963ec878053c6ef0
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
It will return state++ when get the idle state, so we need fill
anothor idle power(=WFI) in the parameter of EAS, code as below:
static int group_idle_state(struct sched_group *sg)
{
int i, state = INT_MAX;
/* Find the shallowest idle state in the sched group. */
for_each_cpu(i, sched_group_cpus(sg))
state = min(state, idle_get_state_idx(cpu_rq(i)));
/* Take non-cpuidle idling into account (active idle/arch_cpu_idle()) */
state++;
return state;
}
Change-Id: I9293da1379746768823df4e75a7478aa50fc0e87
Signed-off-by: Chen Liang <cl@rock-chips.com>
It would be better to name OPP nodes as opp@<opp-hz> as that will ensure
that multiple DT nodes don't contain the same frequency. Of course we
expect the writer to name the node with its opp-hz frequency and not any
other frequency.
And that will let the compile error out if multiple nodes are using the
same opp-hz frequency.
Change-Id: Icefba93f7a95752e344b5a092a83931bf4d1e682
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Some RK3399 evb2 cannot support 1.8G for A72, maybe caused by
current limit, but remove it anyway for evb2.
Change-Id: Ibaa940696ccbdc59131c49e9a643a63863768ea2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
