drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
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- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
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- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
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- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
This commit is contained in:
committed by
Rodrigo Vivi
parent
0069000877
commit
cf819eff90
@@ -344,7 +344,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
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if (INTEL_GEN(dev_priv) >= 10) {
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source_rates = cnl_rates;
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size = ARRAY_SIZE(cnl_rates);
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if (IS_GEN10(dev_priv))
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if (IS_GEN(dev_priv, 10))
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max_rate = cnl_max_source_rate(intel_dp);
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else
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max_rate = icl_max_source_rate(intel_dp);
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@@ -1128,7 +1128,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
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to_i915(intel_dig_port->base.base.dev);
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uint32_t precharge, timeout;
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if (IS_GEN6(dev_priv))
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if (IS_GEN(dev_priv, 6))
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precharge = 3;
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else
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precharge = 5;
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@@ -2585,7 +2585,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
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pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
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pp = ironlake_get_pp_control(intel_dp);
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if (IS_GEN5(dev_priv)) {
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if (IS_GEN(dev_priv, 5)) {
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/* ILK workaround: disable reset around power sequence */
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pp &= ~PANEL_POWER_RESET;
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I915_WRITE(pp_ctrl_reg, pp);
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@@ -2593,7 +2593,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
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}
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pp |= PANEL_POWER_ON;
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if (!IS_GEN5(dev_priv))
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if (!IS_GEN(dev_priv, 5))
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pp |= PANEL_POWER_RESET;
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I915_WRITE(pp_ctrl_reg, pp);
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@@ -2602,7 +2602,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
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wait_panel_on(intel_dp);
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intel_dp->last_power_on = jiffies;
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if (IS_GEN5(dev_priv)) {
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if (IS_GEN(dev_priv, 5)) {
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pp |= PANEL_POWER_RESET; /* restore panel reset bit */
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I915_WRITE(pp_ctrl_reg, pp);
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POSTING_READ(pp_ctrl_reg);
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@@ -2831,7 +2831,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
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* 1. Wait for the start of vertical blank on the enabled pipe going to FDI
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* 2. Program DP PLL enable
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*/
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if (IS_GEN5(dev_priv))
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if (IS_GEN(dev_priv, 5))
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intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
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intel_dp->DP |= DP_PLL_ENABLE;
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@@ -3849,7 +3849,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
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} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
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signal_levels = ivb_cpu_edp_signal_levels(train_set);
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mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
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} else if (IS_GEN6(dev_priv) && port == PORT_A) {
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} else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
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signal_levels = snb_cpu_edp_signal_levels(train_set);
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mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
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} else {
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@@ -5271,17 +5271,17 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
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if (INTEL_GEN(dev_priv) >= 11)
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return icl_digital_port_connected(encoder);
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else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv))
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else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
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return spt_digital_port_connected(encoder);
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else if (IS_GEN9_LP(dev_priv))
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return bxt_digital_port_connected(encoder);
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else if (IS_GEN8(dev_priv))
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else if (IS_GEN(dev_priv, 8))
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return bdw_digital_port_connected(encoder);
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else if (IS_GEN7(dev_priv))
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else if (IS_GEN(dev_priv, 7))
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return ivb_digital_port_connected(encoder);
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else if (IS_GEN6(dev_priv))
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else if (IS_GEN(dev_priv, 6))
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return snb_digital_port_connected(encoder);
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else if (IS_GEN5(dev_priv))
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else if (IS_GEN(dev_priv, 5))
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return ilk_digital_port_connected(encoder);
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MISSING_CASE(INTEL_GEN(dev_priv));
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