mirros/rockchip-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge commit '62646c7ab19511b8fc17078cf4b0603e550e73cd'

Browse Source 
* commit '62646c7ab19511b8fc17078cf4b0603e550e73cd': (119202 commits)
  clk: rockchip: Fix missing rkclk_cpuclk_div_setting prototype for rk3128
  rtc: rk808: Explicitly include of.h for of_get_child_by_name
  ASoC: rk817: Explicitly include gpio/consumer.h for devm_gpiod_get_optional
  drm/rockchip: dsi2: add crtc post enable and pre disable callback
  drm/rockchip: vop2: set dsc config done in crtc post enable
  input: sensors: avoid -Wempty-body warning
  input: sensors: accel: dmard10: Make gsensor_reset() static
  ASoC: rk312x: Fix missing prototypes
  arm64: dts: rockchip: rk3518: Add rockchip,video-1080p-freq for cpu opp table
  soc: rockchip: system_monitor: Add support to limit cpu max freq when play 1080p video
  net: phy: Convert to use sysfs_emit_at() API
  drm/rockchip: dw_hdmi: Explicitly include pinctrl/consumer.h for devm_pinctrl_get
  net: rfkill: bt: Explicitly include pinctrl/consumer.h for pinctrl_select_state
  ASoC: codecs: rk_dsm: Explicitly include pinctrl/consumer.h for devm_pinctrl_get
  spi: rockchip-slave: Explicitly include pinctrl/consumer.h for pinctrl_pm_select_sleep_state
  media: rockchip: isp: Explicitly include platform_device.h
  regulator: rk801: Explicitly include platform_device.h
  soc: rockchip: decompress: Explicitly include of_platform.h for of_platform_device_create
  soc: rockchip: thunderboot_mmc: Explicitly include of_platform.h for of_platform_device_create
  soc: rockchip: thunderboot_sfc: Explicitly include of_platform.h for of_platform_device_create
  ...

Change-Id: I88628746fa5e58f85cf991634fe2f6355ac937e8
This commit is contained in:
Tao Huang
2025-07-04 18:53:19 +08:00
parent a7be916bd9 62646c7ab1
commit aa65b81218
5000 changed files with 3052171 additions and 38238 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
.gitignore vendored
View File

@@ -27,6 +27,7 @@
*.gz
*.i
*.ko
*.lds
*.lex.c
*.ll
*.lst
@@ -57,6 +58,8 @@ modules.order
#
# Top-level generic files
#
/*.img
/out/
/linux
/modules-only.symvers
/vmlinux

348
Documentation/ABI/testing/sysfs-device-mali Normal file
View File

@@ -0,0 +1,348 @@
/*
*
* (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation) and any use by you of this program is subject to the terms
* of such GNU licence.
*
* A copy of the licence is included with the program) and can also be obtained
* from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
* Boston) MA 02110-1301) USA.
*
*/
What: /sys/class/misc/mali%u/device/core_mask
Description:
This attribute is used to restrict the number of shader cores
available in this instance, is useful for debugging purposes.
Reading this attribute provides us mask of all cores available.
Writing to it will set the current core mask. Doesn't
allow disabling all the cores present in this instance.
What: /sys/class/misc/mali%u/device/debug_command
Description:
This attribute is used to issue debug commands that supported
by the driver. On reading it provides the list of debug commands
that are supported, and writing back one of those commands will
enable that debug option.
What: /sys/class/misc/mali%u/device/dvfs_period
Description:
This is used to set the DVFS sampling period to be used by the
driver, On reading it provides the current DVFS sampling period,
on writing a value we set the DVFS sampling period.
What: /sys/class/misc/mali%u/device/dummy_job_wa_info
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU that requires a GPU workaround
to execute the dummy fragment job on all shader cores to
workaround a hang issue.
Its a readonly attribute and on reading gives details on the
options used with the dummy workaround.
What: /sys/class/misc/mali%u/device/fw_timeout
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. This attribute is
used to set the duration value in milliseconds for the
waiting timeout used for a GPU status change request being
acknowledged by the FW.
What: /sys/class/misc/mali%u/device/gpuinfo
Description:
This attribute provides description of the present Mali GPU.
Its a read only attribute provides details like GPU family, the
number of cores, the hardware version and the raw product id.
What: /sys/class/misc/mali%u/device/idle_hysteresis_time
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. This attribute is
used to configure the timeout value in microseconds for the
GPU idle handling. If GPU has been idle for this timeout
period, then it is put to sleep for GPUs where sleep feature
is supported or is powered down after suspending command
stream groups.
What: /sys/class/misc/mali%u/device/idle_hysteresis_time_ns
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. This attribute is
used to configure the timeout value in nanoseconds for the
GPU idle handling. If GPU has been idle for this timeout
period, then it is put to sleep for GPUs where sleep feature
is supported or is powered down after suspending command
stream groups.
What: /sys/class/misc/mali%u/device/js_ctx_scheduling_mode
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. This attribute is used to set
context scheduling priority for a job slot.
On Reading it provides the currently set job slot context
priority.
Writing 0 to this attribute sets it to the mode were
higher priority atoms will be scheduled first, regardless of
the context they belong to. Newly-runnable higher priority atoms
can preempt lower priority atoms currently running on the GPU,
even if they belong to a different context.
Writing 1 to this attribute set it to the mode were the
highest-priority atom will be chosen from each context in turn
using a round-robin algorithm, so priority only has an effect
within the context an atom belongs to. Newly-runnable higher
priority atoms can preempt the lower priority atoms currently
running on the GPU, but only if they belong to the same context.
What: /sys/class/misc/mali%u/device/js_scheduling_period
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. Used to set the job scheduler
tick period in nano-seconds. The Job Scheduler determines the
jobs that are run on the GPU, and for how long, Job Scheduler
makes decisions at a regular time interval determined by value
in js_scheduling_period.
What: /sys/class/misc/mali%u/device/js_softstop_always
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. Soft-stops are disabled when
only a single context is present, this attribute is used to
enable soft-stop when only a single context is present can be
used for debug and unit-testing purposes.
What: /sys/class/misc/mali%u/device/js_timeouts
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. It used to set the soft stop
and hard stop times for the job scheduler.
Writing value 0 causes no change, or -1 to restore the
default timeout.
The format used to set js_timeouts is
"<soft_stop_ms> <soft_stop_ms_cl> <hard_stop_ms_ss>
<hard_stop_ms_cl> <hard_stop_ms_dumping> <reset_ms_ss>
<reset_ms_cl> <reset_ms_dumping>"
What: /sys/class/misc/mali%u/device/lp_mem_pool_max_size
Description:
This attribute is used to set the maximum number of large pages
memory pools that the driver can contain. Large pages are of
size 2MB. On read it displays all the max size of all memory
pools and can be used to modify each individual pools as well.
What: /sys/class/misc/mali%u/device/lp_mem_pool_size
Description:
This attribute is used to set the number of large memory pages
which should be populated, changing this value may cause
existing pages to be removed from the pool, or new pages to be
created and then added to the pool. On read it will provide
pool size for all available pools and we can modify individual
pool.
What: /sys/class/misc/mali%u/device/mem_pool_max_size
Description:
This attribute is used to set the maximum number of small pages
for memory pools that the driver can contain. Here small pages
are of size 4KB. On read it will display the max size for all
available pools and allows us to set max size of
individual pools.
What: /sys/class/misc/mali%u/device/mem_pool_size
Description:
This attribute is used to set the number of small memory pages
which should be populated, changing this value may cause
existing pages to be removed from the pool, or new pages to
be created and then added to the pool. On read it will provide
pool size for all available pools and we can modify individual
pool.
What: /sys/class/misc/mali%u/device/device/mempool/ctx_default_max_size
Description:
This attribute is used to set maximum memory pool size for
all the memory pool so that the maximum amount of free memory
that each pool can hold is identical.
What: /sys/class/misc/mali%u/device/device/mempool/lp_max_size
Description:
This attribute is used to set the maximum number of large pages
for all memory pools that the driver can contain.
Large pages are of size 2MB.
What: /sys/class/misc/mali%u/device/device/mempool/max_size
Description:
This attribute is used to set the maximum number of small pages
for all the memory pools that the driver can contain.
Here small pages are of size 4KB.
What: /sys/class/misc/mali%u/device/pm_poweroff
Description:
This attribute contains the current values, represented as the
following space-separated integers:
• PM_GPU_POWEROFF_TICK_NS.
• PM_POWEROFF_TICK_SHADER.
• PM_POWEROFF_TICK_GPU.
Example:
echo 100000 4 4 > /sys/class/misc/mali0/device/pm_poweroff
Sets the following new values: 100,000ns tick, four ticks
for shader power down, and four ticks for GPU power down.
What: /sys/class/misc/mali%u/device/power_policy
Description:
This attribute is used to find the current power policy been
used, reading will list the power policies available and
enclosed in square bracket is the current one been selected.
Example:
cat /sys/class/misc/mali0/device/power_policy
[demand] coarse_demand always_on
To switch to a different policy at runtime write the valid entry
name back to the attribute.
Example:
echo "coarse_demand" > /sys/class/misc/mali0/device/power_policy
What: /sys/class/misc/mali%u/device/progress_timeout
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. This attribute
is used to set the progress timeout value and read the current
progress timeout value.
Progress timeout value is the maximum number of GPU cycles
without forward progress to allow to elapse before terminating a
GPU command queue group.
What: /sys/class/misc/mali%u/device/mcu_shader_pwroff_timeout
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. The duration value unit
is in micro-seconds and is used for configuring MCU shader Core power-off
timer. The configured MCU shader Core power-off timer will only have
effect when the host driver has delegated the shader cores
power management to MCU. The supplied value will be
recorded internally without any change. But the actual field
value will be subject to core power-off timer source frequency
scaling and maximum value limiting. The default source will be
SYSTEM_TIMESTAMP counter. But in case the platform is not able
to supply it, the GPU CYCLE_COUNTER source will be used as an
alternative.
If we set the value to zero then MCU-controlled shader/tiler
power management will be disabled.
What: /sys/class/misc/mali%u/device/mcu_shader_pwroff_timeout_ns
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. The duration value unit
is in nanoseconds and is used for configuring MCU shader Core power-off
timer. The configured MCU shader Core power-off timer will only have
effect when the host driver has delegated the shader cores
power management to MCU. The supplied value will be
recorded internally without any change. But the actual field
value will be subject to core power-off timer source frequency
scaling and maximum value limiting. The default source will be
SYSTEM_TIMESTAMP counter. But in case the platform is not able
to supply it, the GPU CYCLE_COUNTER source will be used as an
alternative.
If we set the value to zero then MCU-controlled shader/tiler
power management will be disabled.
What: /sys/class/misc/mali%u/device/csg_scheduling_period
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. The duration value unit
is in milliseconds and is used for configuring csf scheduling
tick duration.
What: /sys/class/misc/mali%u/device/reset_timeout
Description:
This attribute is used to set the number of milliseconds to
wait for the soft stop to complete for the GPU jobs before
proceeding with the GPU reset.
What: /sys/class/misc/mali%u/device/soft_job_timeout
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU. It used to set the timeout
value for waiting for any soft event to complete.
What: /sys/class/misc/mali%u/device/scheduling/serialize_jobs
Description:
This attribute is available only with platform device that
supports a Job Manager based GPU.
Various options available under this are:
• none - for disabling serialization.
• intra-slot - Serialize atoms within a slot, only one
atom per job slot.
• inter-slot - Serialize atoms between slots, only one
job slot running at any time.
• full - it a combination of both inter and intra slot,
so only one atom and one job slot running
at any time.
• full-reset - full serialization and Reset the GPU after
each atom completion
These options are useful for debugging and investigating
failures and gpu hangs to narrow down atoms that could cause
troubles.
What: /sys/class/misc/mali%u/device/firmware_config/Compute iterator count/*
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. Its a read-only attribute
which indicates the maximum number of Compute iterators
supported by the GPU.
What: /sys/class/misc/mali%u/device/firmware_config/CSHWIF count/*
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. Its a read-only
attribute which indicates the maximum number of CSHWIFs
supported by the GPU.
What: /sys/class/misc/mali%u/device/firmware_config/Fragment iterator count/*
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. Its a read-only
attribute which indicates the maximum number of
Fragment iterators supported by the GPU.
What: /sys/class/misc/mali%u/device/firmware_config/Scoreboard set count/*
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. Its a read-only
attribute which indicates the maximum number of
Scoreboard set supported by the GPU.
What: /sys/class/misc/mali%u/device/firmware_config/Tiler iterator count/*
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU. Its a read-only
attribute which indicates the maximum number of Tiler iterators
supported by the GPU.
What: /sys/class/misc/mali%u/device/firmware_config/Log verbosity/*
Description:
This attribute is available only with mali platform
device-driver that supports a CSF GPU.
Used to enable firmware logs, logging levels valid values
are indicated using 'min' and 'max' attributes, which are read-only.
Log level can be set using the 'cur' read, write attribute,
we can use a valid log level value from min and max range values
and set a valid desired log level for firmware logs.

203
Documentation/ABI/testing/sysfs-device-mali-coresight-source Normal file
View File

@@ -0,0 +1,203 @@
/*
*
* (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation) and any use by you of this program is subject to the terms
* of such GNU licence.
*
* A copy of the licence is included with the program) and can also be obtained
* from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
* Boston) MA 02110-1301) USA.
*
*/
What: /sys/bus/coresight/devices/mali-source-etm/enable_source
Description:
Attribute used to enable Coresight Source ETM.
What: /sys/bus/coresight/devices/mali-source-etm/is_enabled
Description:
Attribute used to check if Coresight Source ETM is enabled.
What: /sys/bus/coresight/devices/mali-source-etm/trcconfigr
Description:
Coresight Source ETM trace configuration to enable global
timestamping, and data value tracing.
What: /sys/bus/coresight/devices/mali-source-etm/trctraceidr
Description:
Coresight Source ETM trace ID.
What: /sys/bus/coresight/devices/mali-source-etm/trcvdarcctlr
Description:
Coresight Source ETM viewData include/exclude address
range comparators.
What: /sys/bus/coresight/devices/mali-source-etm/trcviiectlr
Description:
Coresight Source ETM viewInst include and exclude control.
What: /sys/bus/coresight/devices/mali-source-etm/trcstallctlr
Description:
Coresight Source ETM stall control register.
What: /sys/bus/coresight/devices/mali-source-itm/enable_source
Description:
Attribute used to enable Coresight Source ITM.
What: /sys/bus/coresight/devices/mali-source-itm/is_enabled
Description:
Attribute used to check if Coresight Source ITM is enabled.
What: /sys/bus/coresight/devices/mali-source-itm/dwt_ctrl
Description:
Coresight Source DWT configuration:
[0] = 1, enable cycle counter
[4:1] = 4, set PC sample rate pf 256 cycles
[8:5] = 1, set initial post count value
[9] = 1, select position of post count tap on the cycle counter
[10:11] = 1, enable sync packets
[12] = 1, enable periodic PC sample packets
What: /sys/bus/coresight/devices/mali-source-itm/itm_tcr
Description:
Coresight Source ITM configuration:
[0] = 1, Enable ITM
[1] = 1, Enable Time stamp generation
[2] = 1, Enable sync packet transmission
[3] = 1, Enable HW event forwarding
[11:10] = 1, Generate TS request approx every 128 cycles
[22:16] = 1, Trace bus ID
What: /sys/bus/coresight/devices/mali-source-ela/reset_regs
Description:
Attribute used to reset registers to zero.
What: /sys/bus/coresight/devices/mali-source-ela/enable_source
Description:
Attribute used to enable Coresight Source ELA.
What: /sys/bus/coresight/devices/mali-source-ela/is_enabled
Description:
Attribute used to check if Coresight Source ELA is enabled.
What: /sys/bus/coresight/devices/mali-source-ela/regs/TIMECTRL
Description:
Coresight Source ELA TIMECTRL register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/TSSR
Description:
Coresight Source ELA TSR register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/ATBCTRL
Description:
Coresight Source ELA ATBCTRL register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/PTACTION
Description:
Coresight Source ELA PTACTION register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/AUXCTRL
Description:
Coresight Source ELA AUXCTRL register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/CNTSEL
Description:
Coresight Source ELA CNTSEL register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/SIGSELn
Description:
Coresight Source ELA SIGSELn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/TRIGCTRLn
Description:
Coresight Source ELA TRIGCTRLn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/NEXTSTATEn
Description:
Coresight Source ELA NEXTSTATEn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/ACTIONn
Description:
Coresight Source ELA ACTIONn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/ALTNEXTSTATEn
Description:
Coresight Source ELA ALTNEXTSTATEn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/ALTACTIONn
Description:
Coresight Source ELA ALTACTIONn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/COMPCTRLn
Description:
Coresight Source ELA COMPCTRLn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/ALTCOMPCTRLn
Description:
Coresight Source ELA ALTCOMPCTRLn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/COUNTCOMPn
Description:
Coresight Source ELA COUNTCOMPn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/TWBSELn
Description:
Coresight Source ELA TWBSELn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/EXTMASKn
Description:
Coresight Source ELA EXTMASKn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/EXTCOMPn
Description:
Coresight Source ELA EXTCOMPn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/QUALMASKn
Description:
Coresight Source ELA QUALMASKn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/QUALCOMPn
Coresight Source ELA QUALCOMPn register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/SIGMASKn_0-7
Description:
Coresight Source ELA SIGMASKn_0-7 register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/SIGCOMPn_0-7
Description:
Coresight Source ELA SIGCOMPn_0-7 register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/SIGSELn_0-7
Description:
Coresight Source ELA SIGSELn_0-7 register set/get.
Refer to specification for more details.
What: /sys/bus/coresight/devices/mali-source-ela/regs/SIGMASKn_0-7
Description:
Coresight Source ELA SIGMASKn_0-7 register set/get.
Refer to specification for more details.

58
Documentation/admin-guide/pm/cpufreq.rst
View File

@@ -590,6 +590,64 @@ This governor exposes the following tunables:
It effectively causes the frequency to go down ``sampling_down_factor``
times slower than it ramps up.
``interactive``
----------------
The CPUfreq governor `interactive` is designed for latency-sensitive,
interactive workloads. This governor sets the CPU speed depending on
usage, similar to `ondemand` and `conservative` governors, but with a
different set of configurable behaviors.
The tunable values for this governor are:
``above_hispeed_delay``
When speed is at or above hispeed_freq, wait for
this long before raising speed in response to continued high load.
The format is a single delay value, optionally followed by pairs of
CPU speeds and the delay to use at or above those speeds. Colons can
be used between the speeds and associated delays for readability. For
example:
80000 1300000:200000 1500000:40000
uses delay 80000 uS until CPU speed 1.3 GHz, at which speed delay
200000 uS is used until speed 1.5 GHz, at which speed (and above)
delay 40000 uS is used. If speeds are specified these must appear in
ascending order. Default is 20000 uS.
``boost``
If non-zero, immediately boost speed of all CPUs to at least
hispeed_freq until zero is written to this attribute. If zero, allow
CPU speeds to drop below hispeed_freq according to load as usual.
Default is zero.
``boostpulse``
On each write, immediately boost speed of all CPUs to
hispeed_freq for at least the period of time specified by
boostpulse_duration, after which speeds are allowed to drop below
hispeed_freq according to load as usual. Its a write-only file.
``boostpulse_duration``
Length of time to hold CPU speed at hispeed_freq
on a write to boostpulse, before allowing speed to drop according to
load as usual. Default is 80000 uS.
``go_hispeed_load``
The CPU load at which to ramp to hispeed_freq.
Default is 99%.
``hispeed_freq``
An intermediate "high speed" at which to initially ramp
when CPU load hits the value specified in go_hispeed_load. If load
stays high for the amount of time specified in above_hispeed_delay,
then speed may be bumped higher. Default is the maximum speed allowed
by the policy at governor initialization time.
``io_is_busy``
If set, the governor accounts IO time as CPU busy time.
``min_sample_time``
The minimum amount of time to spend at the current
Frequency Boost Support
=======================

173
Documentation/csf_sync_state_dump.txt Normal file
View File

@@ -0,0 +1,173 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2022-2023 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
DebugFS interface:
------------------
A new per-kbase-context debugfs file called csf_sync has been implemented
which captures the current KCPU & GPU queue state of the not-yet-completed
operations and displayed through the debugfs file.
This file is at:
=======================================================
/sys/kernel/debug/mali0/ctx/<pid>_<context id>/csf_sync
=======================================================
Output Format:
----------------
The csf_sync file contains important data for the currently active queues.
This data is formatted into two segments, which are separated by a
pipe character: the common properties and the operation-specific properties.
Common Properties:
------------------
* Queue type: GPU or KCPU.
* kbase context id and the queue id.
* If the queue type is a GPU queue then the group handle is also noted,
in the middle of the other two IDs. The slot value is also dumped.
* Execution status, which can either be 'P' for pending or 'S' for started.
* Command type is then output which indicates the type of dependency
(i.e. wait or signal).
* Object address which is a pointer to the sync object that the
command operates on.
* The live value, which is the value of the synchronization object
at the time of dumping. This could help to determine why wait
operations might be blocked.
Operation-Specific Properties:
------------------------------
The operation-specific values for KCPU queue fence operations
are as follows: a unique timeline name, timeline context, and a fence
sequence number. The CQS WAIT and CQS SET are denoted in the sync dump
as their OPERATION counterparts, and therefore show the same operation
specific values; the argument value to wait on or set to, and operation type,
being (by definition) op:gt and op:set for CQS_WAIT and CQS_SET respectively.
There are only two operation-specific values for operations in GPU queues
which are always shown; the argument value to wait on or set/add to,
and the operation type (set/add) or wait condition (e.g. LE, GT, GE).
Examples
--------
GPU Queue Example
------------------
The following output is of a GPU queue, from a process that has a KCTX ID of 52,
is in Queue Group (CSG) 0, and has Queue ID 0. It has started and is waiting on
the object at address 0x0000007f81ffc800. The live value is 0,
as is the arg value. However, the operation "op" is GT, indicating it's waiting
for the live value to surpass the arg value:
======================================================================================================================================
queue:GPU-52-0-0 exec:S cmd:SYNC_WAIT slot:4 obj:0x0000007f81ffc800 live_value:0x0000000000000000 | op:gt arg_value:0x0000000000000000
======================================================================================================================================
The following is an example of GPU queue dump, where the SYNC SET operation
is blocked by the preceding SYNC WAIT operation. This shows two GPU queues,
with the same KCTX ID of 8, Queue Group (CSG) 0, and Queue ID 0. The SYNC WAIT
operation has started, while the SYNC SET is pending, blocked by the SYNC WAIT.
Both operations are on the same slot, 2 and have live value of 0. The SYNC WAIT
is waiting on the object at address 0x0000007f81ffc800, while the SYNC SET will
set the object at address 0x00000000a3bad4fb when it is unblocked.
The operation "op" is GT for the SYNC WAIT, indicating it's waiting for the
live value to surpass the arg value, while the operation and arg value for the
SYNC SET is "set" and "1" respectively:
======================================================================================================================================
queue:GPU-8-0-0 exec:S cmd:SYNC_WAIT slot:2 obj:0x0000007f81ffc800 live_value:0x0000000000000000 | op:gt arg_value:0x0000000000000000
queue:GPU-8-0-0 exec:P cmd:SYNC_SET slot:2 obj:0x00000000a3bad4fb live_value:0x0000000000000000 | op:set arg_value:0x0000000000000001
======================================================================================================================================
KCPU Queue Example
------------------
The following is an example of a KCPU queue, from a process that has
a KCTX ID of 0 and has Queue ID 1. It has started and is waiting on the
object at address 0x0000007fbf6f2ff8. The live value is currently 0 with
the "op" being GT indicating it is waiting on the live value to
surpass the arg value.
===============================================================================================================================
queue:KCPU-0-1 exec:S cmd:CQS_WAIT_OPERATION obj:0x0000007fbf6f2ff8 live_value:0x0000000000000000 | op:gt arg_value: 0x00000000
===============================================================================================================================
CSF Sync State Dump For Fence Signal Timeouts
---------------------------------------------
Summary
-------
A timer has been added to the KCPU queues which is checked to ensure
the queues have not "timed out" between the enqueuing of a fence signal command
and it's eventual execution. If this timeout happens then the CSF sync state
of all KCPU queues of the offending context is dumped. This feature is enabled
by default, but can be disabled/enabled later.
Explanation
------------
This new timer is created and destroyed alongside the creation and destruction
of each KCPU queue. It is started when a fence signal is enqueued, and cancelled
when the fence signal command has been processed. The timer times out after
10 seconds (at 100 MHz) if the execution of that fence signal event was never
processed. If this timeout occurs then the timer callback function identifies
the KCPU queue which the timer belongs to and invokes the CSF synchronisation
state dump mechanism, writing the sync state for the context of the queue
causing the timeout is dump to dmesg.
Fence Timeouts Controls
-----------------------
Disable/Enable Feature
----------------------
This feature is enabled by default, but can be disabled/ re-enabled via DebugFS
controls. The 'fence_signal_timeout_enable' debugfs entry is a global flag
which is written to, to turn this feature on and off.
Example:
--------
when writing to fence_signal_timeout_enable entry:
echo 1 > /sys/kernel/debug/mali0/fence_signal_timeout_enable -> feature is enabled.
echo 0 > /sys/kernel/debug/mali0/fence_signal_timeout_enable -> feature is disabled.
It is also possible to read from this file to check if the feature is currently
enabled or not checking the return value of fence_signal_timeout_enable.
Example:
--------
when reading from fence_signal_timeout_enable entry, if:
cat /sys/kernel/debug/mali0/fence_signal_timeout_enable returns 1 -> feature is enabled.
cat /sys/kernel/debug/mali0/fence_signal_timeout_enable returns 0 -> feature is disabled.
Update Timer Duration
---------------------
The timeout duration can be accessed through the 'fence_signal_timeout_ms'
debugfs entry. This can be read from to retrieve the current time in
milliseconds.
Example:
--------
cat /sys/kernel/debug/mali0/fence_signal_timeout_ms
The 'fence_signal_timeout_ms' debugfs entry can also be written to, to update
the time in milliseconds.
Example:
--------
echo 10000 > /sys/kernel/debug/mali0/fence_signal_timeout_ms

163
Documentation/devicetree/bindings/arm/arm,coresight-mali-source.yaml Normal file
View File

@@ -0,0 +1,163 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2022-2024 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-mali-source.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM CoreSight Mali Source integration
maintainers:
- ARM Ltd.
description: |
See Documentation/trace/coresight/coresight.rst for detailed information
about Coresight.
This documentation will cover Mali specific devicetree integration.
References to Sink ports are given as examples. Access to Sink is specific
to an implementation and would require dedicated kernel modules.
Arm Mali GPU are supporting 3 different sources: ITM, ETM, ELA
ELA source configuration via SysFS entries:
The register values used by CoreSight for ELA can be configured using SysFS
interfaces. This implicitly includes configuring the ELA for independent or
shared JCN request and response channels.
properties:
compatible:
enum:
- arm,coresight-mali-source-itm
- arm,coresight-mali-source-etm
- arm,coresight-mali-source-ela
gpu:
minItems: 1
maxItems: 1
description:
Phandle to a Mali GPU definition
port:
description:
Output connection to CoreSight Sink Trace bus.
Legacy binding between Coresight Sources and CoreSight Sink.
For Linux kernel < v4.20.
$ref: /schemas/graph.yaml#/properties/port
out-ports:
description:
Binding between Coresight Sources and CoreSight Sink.
For Linux kernel >= v4.20.
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Output connection to CoreSight Sink Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- gpu
- port
- out-ports
additionalProperties: false
examples:
# A Sink node without legacy CoreSight connections
- |
mali-source-itm {
compatible = "arm,coresight-mali-source-itm";
gpu = <&gpu>;
out-ports {
port {
mali_source_itm_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port0>;
};
};
};
};
mali-source-ela {
compatible = "arm,coresight-mali-source-ela";
gpu = <&gpu>;
out-ports {
port {
mali_source_ela_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port1>;
};
};
};
};
mali-source-etm {
compatible = "arm,coresight-mali-source-etm";
gpu = <&gpu>;
out-ports {
port {
mali_source_etm_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port2>;
};
};
};
};
# A Sink node with legacy CoreSight connections
- |
mali-source-itm {
compatible = "arm,coresight-mali-source-itm";
gpu = <&gpu>;
port {
mali_source_itm_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port0>;
};
};
};
mali-source-etm {
compatible = "arm,coresight-mali-source-etm";
gpu = <&gpu>;
port {
mali_source_etm_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port1>;
};
};
};
mali-source-ela {
compatible = "arm,coresight-mali-source-ela";
gpu = <&gpu>;
port {
mali_source_ela_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port2>;
};
};
};

251
Documentation/devicetree/bindings/arm/mali-bifrost.txt Normal file
View File

@@ -0,0 +1,251 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2013-2024 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
* ARM Mali Midgard / Bifrost devices
Required properties:
- compatible : Should be mali<chip>, replacing digits with x from the back,
until malit<Major>xx, and it must end with one of: "arm,malit6xx" or
"arm,mali-midgard" or "arm,mali-bifrost"
- reg : Physical base address of the device and length of the register area.
- interrupts : Contains the three IRQ lines required by T-6xx devices
- interrupt-names : Contains the names of IRQ resources in the order they were
provided in the interrupts property. Must contain: "JOB, "MMU", "GPU".
Optional:
- clocks : One or more pairs of phandle to clock and clock specifier
for the Mali device. The order is important: the first clock
shall correspond to the "clk_mali" source, while the second clock
(that is optional) shall correspond to the "shadercores" source.
- clock-names : Shall be set to: "clk_mali", "shadercores".
- mali-supply : Phandle to the top level regulator for the Mali device.
Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- mem-supply : Phandle to memory regulator for the Mali device. This is optional.
- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/mali-opp.txt
for details.
- quirks-gpu : Used to write to the JM_CONFIG or CSF_CONFIG register.
Should be used with care. Options passed here are used to override
certain default behavior. Note: This will override 'idvs-group-size'
field in devicetree and module param 'corestack_driver_control',
therefore if 'quirks-gpu' is used then 'idvs-group-size' and
'corestack_driver_control' value should be incorporated into 'quirks-gpu'.
- quirks-sc : Used to write to the SHADER_CONFIG register.
Should be used with care. Options passed here are used to override
certain default behavior.
- quirks-tiler : Used to write to the TILER_CONFIG register.
Should be used with care. Options passed here are used to
disable or override certain default behavior.
- quirks-mmu : Used to write to the L2_CONFIG register.
Should be used with care. Options passed here are used to
disable or override certain default behavior.
- power-model : Sets the power model parameters. Defined power models include:
"mali-simple-power-model", "mali-g51-power-model", "mali-g52-power-model",
"mali-g52_r1-power-model", "mali-g71-power-model", "mali-g72-power-model",
"mali-g76-power-model", "mali-g77-power-model", "mali-tnax-power-model",
"mali-tbex-power-model" and "mali-tbax-power-model".
- mali-simple-power-model: this model derives the GPU power usage based
on the GPU voltage scaled by the system temperature. Note: it was
designed for the Juno platform, and may not be suitable for others.
- compatible: Should be "arm,mali-simple-power-model"
- dynamic-coefficient: Coefficient, in pW/(Hz V^2), which is
multiplied by v^2*f to calculate the dynamic power consumption.
- static-coefficient: Coefficient, in uW/V^3, which is
multiplied by v^3 to calculate the static power consumption.
- ts: An array containing coefficients for the temperature
scaling factor. This is used to scale the static power by a
factor of tsf/1000000,
where tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0],
and T = temperature in degrees.
- thermal-zone: A string identifying the thermal zone used for
the GPU
- temp-poll-interval-ms: the interval at which the system
temperature is polled
- mali-g*-power-model(s): unless being stated otherwise, these models derive
the GPU power usage based on performance counters, so they are more
accurate.
- compatible: Should be, as examples, "arm,mali-g51-power-model" /
"arm,mali-g72-power-model".
- scale: the dynamic power calculated by the power model is
multiplied by a factor of 'scale'. This value should be
chosen to match a particular implementation.
- min_sample_cycles: Fall back to the simple power model if the
number of GPU cycles for a given counter dump is less than
'min_sample_cycles'. The default value of this should suffice.
* Note: when IPA is used, two separate power models (simple and counter-based)
are used at different points so care should be taken to configure
both power models in the device tree (specifically dynamic-coefficient,
static-coefficient and scale) to best match the platform.
- power-policy : Sets the GPU power policy at probe time. Available options are
"coarse_demand" and "always_on". If not set, then "coarse_demand" is used.
- system-coherency : Sets the coherency protocol to be used for coherent
accesses made from the GPU.
If not set then no coherency is used.
- 0 : ACE-Lite
- 1 : ACE
- 31 : No coherency
- ipa-model : Sets the IPA model to be used for power management. GPU probe will fail if the
model is not found in the registered models list. If no model is specified here,
a gpu-id based model is picked if available, otherwise the default model is used.
- mali-simple-power-model: Default model used on mali
- idvs-group-size : Override the IDVS group size value. Tasks are sent to
cores in groups of N + 1, so i.e. 0xF means 16 tasks.
Valid values are between 0 to 0x3F (including).
- l2-size : Override L2 cache size on GPU that supports it. Value should be larger than the minimum
size 1KiB and smaller than the maximum size. Maximum size is Hardware integration dependent.
The value passed should be of log2(Cache Size in Bytes).
For example for a 1KiB of cache size, 0xa should be passed.
- l2-hash : Override L2 hash function on GPU that supports it
- l2-hash-values : Override L2 hash function using provided hash values, on GPUs that supports it.
It is mutually exclusive with 'l2-hash'. Only one or the other must be
used in a supported GPU.
- arbiter-if : Phandle to the arbif platform device, used to provide KBASE with an interface
to the Arbiter. This is required when using arbitration; setting to a non-NULL
value will enable arbitration.
If arbitration is in use, then there should be no external GPU control.
When arbiter-if is in use then the following must not be:
- power-model (no IPA allowed with arbitration)
- #cooling-cells
- operating-points-v2 (no dvfs in kbase with arbitration)
- system-coherency with a value of 1 (no full coherency with arbitration)
- int-id-override: list of <ID Setting[7:0]> tuples defining the IDs needed to be
set and the setting coresponding to the SYSC_ALLOC register.
- propagate-bits: Used to write to L2_CONFIG.PBHA_HWU. This bitset establishes which
PBHA bits are propagated on the AXI bus.
- mma-wa-id: Sets the PBHA ID to be used for the PBHA override based MMA violation workaround.
The read and write allocation override bits for the PBHA are set to NONCACHEABLE
and the driver encodes the PBHA ID in the PTEs where this workaround is to be applied.
Valid values are from 1 to 15.
Example for a Mali GPU with 1 clock and 1 regulator:
gpu@0xfc010000 {
compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
reg = <0xfc010000 0x4000>;
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&pclk_mali>;
clock-names = "clk_mali";
mali-supply = <&vdd_mali>;
operating-points-v2 = <&gpu_opp_table>;
power_model@0 {
compatible = "arm,mali-simple-power-model";
static-coefficient = <2427750>;
dynamic-coefficient = <4687>;
ts = <20000 2000 (-20) 2>;
thermal-zone = "gpu";
};
power_model@1 {
compatible = "arm,mali-g71-power-model";
scale = <5>;
};
idvs-group-size = <0x7>;
l2-size = /bits/ 8 <0x10>;
l2-hash = /bits/ 8 <0x04>; /* or l2-hash-values = <0x12345678 0x8765 0xAB>; */
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp@533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
opp@450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp@266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp@160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <912500>;
};
};
Example for a Mali GPU with 2 clocks and 2 regulators:
gpu: gpu@6e000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x6e000000 0x0 0x200000>;
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&clk_mali 0>, <&clk_mali 1>;
clock-names = "clk_mali", "shadercores";
mali-supply = <&supply0_3v3>;
mem-supply = <&supply1_3v3>;
system-coherency = <31>;
operating-points-v2 = <&gpu_opp_table>;
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2", "operating-points-v2-mali";
opp@0 {
opp-hz = /bits/ 64 <50000000>;
opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>;
opp-microvolt = <820000>, <800000>;
opp-core-mask = /bits/ 64 <0xf>;
};
opp@1 {
opp-hz = /bits/ 64 <40000000>;
opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>;
opp-microvolt = <720000>, <700000>;
opp-core-mask = /bits/ 64 <0x7>;
};
opp@2 {
opp-hz = /bits/ 64 <30000000>;
opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>;
opp-microvolt = <620000>, <700000>;
opp-core-mask = /bits/ 64 <0x3>;
};
};
Example for a Mali GPU supporting PBHA configuration via DTB (default):
gpu@0xfc010000 {
...
pbha {
int-id-override = <2 0x32>, <9 0x05>, <16 0x32>;
propagate-bits = /bits/ 8 <0x03>;
mma-wa-id = <2>;
};
...
};

116
Documentation/devicetree/bindings/arm/mali-coresight-source.txt Normal file
View File

@@ -0,0 +1,116 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2023 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
=====================================
ARM CoreSight Mali Source integration
=====================================
See Documentation/trace/coresight/coresight.rst for detailed information
about Coresight.
This documentation will cover Mali specific devicetree integration.
References to Sink ports are given as examples. Access to Sink is specific
to an implementation and would require dedicated kernel modules.
ARM Coresight Mali Source ITM
=============================
Required properties
-------------------
- compatible: Has to be "arm,coresight-mali-source-itm"
- gpu : phandle to a Mali GPU definition
- port:
- endpoint:
- remote-endpoint: phandle to a Coresight sink port
Example
-------
mali-source-itm {
compatible = "arm,coresight-mali-source-itm";
gpu = <&gpu>;
port {
mali_source_itm_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port0>;
};
};
};
ARM Coresight Mali Source ETM
=============================
Required properties
-------------------
- compatible: Has to be "arm,coresight-mali-source-etm"
- gpu : phandle to a Mali GPU definition
- port:
- endpoint:
- remote-endpoint: phandle to a Coresight sink port
Example
-------
mali-source-etm {
compatible = "arm,coresight-mali-source-etm";
gpu = <&gpu>;
port {
mali_source_etm_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port1>;
};
};
};
ARM Coresight Mali Source ELA
=============================
Required properties
-------------------
- compatible: Has to be "arm,coresight-mali-source-ela"
- gpu : phandle to a Mali GPU definition
- port:
- endpoint:
- remote-endpoint: phandle to a Coresight sink port
Example: Split JCN request/response channel
--------------------------------------------
This examples applies to implementations with a total of 5 signal groups,
where JCN request and response are assigned to independent or shared
channels depending on the GPU model.
mali-source-ela {
compatible = "arm,coresight-mali-source-ela";
gpu = <&gpu>;
port {
mali_source_ela_out_port0: endpoint {
remote-endpoint = <&mali_sink_in_port2>;
};
};
};
SysFS Configuration
--------------------------------------------
The register values used by CoreSight for ELA can be configured using SysFS
interfaces. This implicitly includes configuring the ELA for independent or
shared JCN request and response channels.

96
Documentation/devicetree/bindings/arm/mali-midgard.txt Normal file
View File

@@ -0,0 +1,96 @@
#
# (C) COPYRIGHT 2013-2017 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU licence.
#
# A copy of the licence is included with the program, and can also be obtained
# from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
# Boston, MA 02110-1301, USA.
#
#
* ARM Mali Midgard devices
Required properties:
- compatible : Should be mali<chip>, replacing digits with x from the back,
until malit<Major>xx, ending with arm,mali-midgard, the latter not optional.
- reg : Physical base address of the device and length of the register area.
- interrupts : Contains the three IRQ lines required by T-6xx devices
- interrupt-names : Contains the names of IRQ resources in the order they were
provided in the interrupts property. Must contain: "JOB, "MMU", "GPU".
Optional:
- clocks : Phandle to clock for the Mali T-6xx device.
- clock-names : Shall be "clk_mali".
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.
- operating-points : Refer to Documentation/devicetree/bindings/power/opp.txt
for details.
- jm_config : For T860/T880. Sets job manager configuration. An array containing:
- 1 to override the TIMESTAMP value, 0 otherwise.
- 1 to override clock gate, forcing them to be always on, 0 otherwise.
- 1 to enable job throttle, limiting the number of cores that can be started
simultaneously, 0 otherwise.
- Value between 0 and 63 (including). If job throttle is enabled, this is one
less than the number of cores that can be started simultaneously.
- power_model : Sets power model parameters. Note that this model was designed for the Juno
platform, and may not be suitable for other platforms. A structure containing :
- compatible: Should be arm,mali-simple-power-model
- dynamic-coefficient: Coefficient, in pW/(Hz V^2), which is multiplied
by v^2*f to calculate the dynamic power consumption.
- static-coefficient: Coefficient, in uW/V^3, which is multiplied by
v^3 to calculate the static power consumption.
- ts: An array containing coefficients for the temperature scaling
factor. This is used to scale the static power by a factor of
tsf/1000000, where tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0],
and T = temperature in degrees.
- thermal-zone: A string identifying the thermal zone used for the GPU
- system-coherency : Sets the coherency protocol to be used for coherent
accesses made from the GPU.
If not set then no coherency is used.
- 0 : ACE-Lite
- 1 : ACE
- 31 : No coherency
- ipa-model : Sets the IPA model to be used for power management. GPU probe will fail if the
model is not found in the registered models list. If no model is specified here,
a gpu-id based model is picked if available, otherwise the default model is used.
- mali-simple-power-model: Default model used on mali
- protected-mode-switcher : Phandle to device implemented protected mode switching functionality.
Refer to Documentation/devicetree/bindings/arm/smc-protected-mode-switcher.txt for one implementation.
Example for a Mali-T602:
gpu@0xfc010000 {
compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
reg = <0xfc010000 0x4000>;
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&pclk_mali>;
clock-names = "clk_mali";
mali-supply = <&vdd_mali>;
operating-points = <
/* KHz uV */
533000 1250000,
450000 1150000,
400000 1125000,
350000 1075000,
266000 1025000,
160000 925000,
100000 912500,
>;
power_model {
compatible = "arm,mali-simple-power-model";
static-coefficient = <2427750>;
dynamic-coefficient = <4687>;
ts = <20000 2000 (-20) 2>;
thermal-zone = "gpu";
};
};

68
Documentation/devicetree/bindings/arm/mali-utgard.txt Normal file
View File

@@ -0,0 +1,68 @@
/*
* Copyright (C) 2014, 2016-2017 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
*
* A copy of the licence is included with the program, and can also be obtained from Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
* ARM Mali-300/400/450 GPU
Required properties:
- compatible:
At least one of these: "arm,mali-300", "arm,mali-400", "arm,mali-450"
Always: "arm,mali-utgard"
Mali-450 can also include "arm,mali-400" as it is compatible.
- "arm,mali-400", "arm,mali-utgard" for any Mali-400 GPU.
- "arm,mali-450", "arm,mali-400", "arm,mali-utgard" for any Mali-450 GPU.
- reg:
Physical base address and length of the GPU's registers.
- interrupts:
- List of all Mali interrupts.
- This list must match the number of and the order of entries in
interrupt-names.
- interrupt-names:
- IRQPP<X> - Name for PP interrupts.
- IRQPPMMU<X> - Name for interrupts from the PP MMU.
- IRQPP - Name for the PP broadcast interrupt (Mali-450 only).
- IRQGP - Name for the GP interrupt.
- IRQGPMMU - Name for the interrupt from the GP MMU.
- IRQPMU - Name for the PMU interrupt (If pmu is implemented in HW, it must be contained).
Optional properties:
- pmu_domain_config:
- If the Mali internal PMU is present and the PMU IRQ is specified in
interrupt/interrupt-names ("IRQPMU").This contains the mapping of
Mali HW units to the PMU power domain.
-Mali Dynamic power domain configuration in sequence from 0-11, like:
<GP PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 L2$0 L2$1 L2$2>.
- pmu-switch-delay:
- Only needed if the power gates are connected to the PMU in a high fanout
network. This value is the number of Mali clock cycles it takes to
enable the power gates and turn on the power mesh. This value will
have no effect if a daisy chain implementation is used.
Platform related properties:
- clocks: Phandle to clock for Mali utgard device.
- clock-names: the corresponding names of clock in clocks property.
- regulator: Phandle to regulator which is power supplier of mali device.
Example for a Mali400_MP1_PMU device:
/ {
...
gpu@12300000 {
compatible = "arm,mali-400", "arm,mali-utgard";
reg = <0x12300000 0x30000>;
interrupts = <0 55 4>, <0 56 4>, <0 57 4>, <0 58 4>, <0 59 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPMU";
pmu_domain_config = <0x1 0x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2 0x0 0x0>;
pmu_switch_delay = <0xff>;
clocks = <clock 122>, <clock 123>;
clock-names = "mali_parent", "mali";
vdd_g3d-supply = <regulator_Phandle>;
};
}

48
Documentation/devicetree/bindings/arm/memory_group_manager.txt Normal file
View File

@@ -0,0 +1,48 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
* Arm memory group manager for Mali GPU device drivers
Required properties:
- compatible: Must be "arm,physical-memory-group-manager"
An example node:
gpu_physical_memory_group_manager: physical-memory-group-manager {
compatible = "arm,physical-memory-group-manager";
};
It must be referenced by the GPU as well, see physical-memory-group-manager:
gpu: gpu@0x6e000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x6e000000 0x0 0x200000>;
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&scpi_dvfs 2>;
clock-names = "clk_mali";
system-coherency = <31>;
physical-memory-group-manager = <&gpu_physical_memory_group_manager>;
operating-points = <
/* KHz uV */
50000 820000
>;
};

48
Documentation/devicetree/bindings/arm/priority_control_manager.txt Normal file
View File

@@ -0,0 +1,48 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
* Arm priority control manager for Mali GPU device drivers
Required properties:
- compatible: Must be "arm,priority-control-manager"
An example node:
gpu_priority_control_manager: priority-control-manager {
compatible = "arm,priority-control-manager";
};
It must be referenced by the GPU as well, see priority-control-manager:
gpu: gpu@0x6e000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x6e000000 0x0 0x200000>;
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&scpi_dvfs 2>;
clock-names = "clk_mali";
system-coherency = <31>;
priority-control-manager = <&gpu_priority_control_manager>;
operating-points = <
/* KHz uV */
50000 820000
>;
};

68
Documentation/devicetree/bindings/arm/protected_memory_allocator.txt Normal file
View File

@@ -0,0 +1,68 @@
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
#
# (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
#
# This program is free software and is provided to you under the terms of the
# GNU General Public License version 2 as published by the Free Software
# Foundation, and any use by you of this program is subject to the terms
# of such GNU license.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, you can access it online at
# http://www.gnu.org/licenses/gpl-2.0.html.
#
#
* Arm protected memory allocator for Mali GPU device drivers
Required properties:
- compatible: Must be "arm,protected-memory-allocator"
The protected memory allocator manages allocation of physical pages of a
reserved memory region of protected memory, therefore its device node shall
reference a reserved memory region.
In addition to that, the protected memory allocator shall be referenced
by the GPU.
A complete example configuration for the device tree:
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
mali_protected: mali_protected@c0000000 {
compatible = "mali-reserved";
reg = <0x0 0xc0000000 0x0 0x1000000>;
};
};
gpu_protected_memory_allocator: protected-memory-allocator {
compatible = "arm,protected-memory-allocator";
memory-region = <&mali_protected>;
};
gpu_fpga: gpu@0x6e000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x6e000000 0x0 0x200000>;
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&scpi_dvfs 2>;
clock-names = "clk_mali";
protected-memory-allocator = <&gpu_protected_memory_allocator>;
operating-points = <
/* KHz uV */
50000 820000
>;
};
The protected memory allocator is gpu_protected_memory_allocator.
It references the mali_protected reserved memory region and, in turn,
it is referenced by the GPU as protected-memory-allocator.

24
Documentation/devicetree/bindings/clock/clk-pvtm.txt Normal file
View File

@@ -0,0 +1,24 @@
ROCKCHIP PVTM 32KHz clocks *
ROCKCHIP device has two clock sources for 32KHz, external 32k osc and internal pvtm 32k.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : "rockchip,rk3368-pvtm-clock" for rk3368 soc pvtm 32k clock
- #clock-cells : shall be set to 0.
Optional property:
- clock-output-names : From common clock binding.
Example:
pvtm_clock: pvtm-clock {
compatible = "rockchip,rk3368-pvtm-clock";
#clock-cells = <0>;
clocks = <&cru SCLK_PVTM_PMU>;
clock-names = "pvtm_pmu_clk";
clock-output-names = "xin32k_pvtm";
status = "okay";
};

107
Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml Normal file
View File

@@ -0,0 +1,107 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip Clock Out Control Module Binding
maintainers:
- Sugar Zhang <sugar.zhang@rock-chips.com>
description: |
This add support switch for clk-bidirection which located
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
and these config maybe located in many pieces of GRF,
which hard to addressed in one single clk driver. so, we add
this simple helper driver to address this situation.
In order to simplify implement and usage, and also for safety
clk usage (avoid high freq glitch), we set all clk out as disabled
(which means Input default for clk-bidrection) in the pre-stage,
such boot-loader or init by HW default. And then set a safety freq
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
in drivers.
properties:
compatible:
enum:
- rockchip,clk-out
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
maxItems: 1
description: parent clocks.
power-domains:
maxItems: 1
clock-output-names:
maxItems: 1
rockchip,bit-shift:
$ref: /schemas/types.yaml#/definitions/uint32
description: Defines the bit shift of clk out enable.
rockchip,bit-set-to-disable:
type: boolean
description: |
By default this clock sets the bit at bit-shift to enable the clock.
Setting this property does the opposite: setting the bit disable
the clock and clearing it enables the clock.
required:
- compatible
- reg
- clocks
- "#clock-cells"
- clock-output-names
- rockchip,bit-shift
additionalProperties: false
examples:
# Clock Provider node:
- |
mclkin_sai0: mclkin-sai0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "mclk_sai0_from_io";
};
mclkout_sai0: mclkout-sai0@ff040070 {
compatible = "rockchip,clk-out";
reg = <0 0xff040070 0 0x4>;
clocks = <&cru MCLK_SAI0_OUT2IO>;
#clock-cells = <0>;
clock-output-names = "mclk_sai0_to_io";
rockchip,bit-shift = <4>;
};
# Clock mclkout Consumer node:
- |
ext_codec {
clocks = <&mclkout_sai0>;
clock-names = "mclk";
assigned-clocks = <&mclkout_sai0>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};
# Clock mclkin Consumer node:
- |
ext_codec {
clocks = <&mclkin_sai0>;
clock-names = "mclk";
assigned-clocks = <&cru CLK_SAI0>;
assigned-clock-parents = <&mclkin_sai0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};

53
Documentation/devicetree/bindings/clock/rockchip,rk1808-cru.txt Normal file
View File

@@ -0,0 +1,53 @@
* Rockchip RK1808 Clock and Reset Unit
The RK1808 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk1808-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk1808-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "mclk_i2s0_8ch_in" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
Example: Clock controller node:
cru: clock-controller@ff350000 {
compatible = "rockchip,rk1808-cru";
reg = <0x0 0xff350000 0x0 0x5000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart1: serial@ff540000 {
compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
reg = <0x0 0xff540000 0x0 0x100>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
};

58
Documentation/devicetree/bindings/clock/rockchip,rk3308.txt Normal file
View File

@@ -0,0 +1,58 @@
* Rockchip RK3308 Clock and Reset Unit
The RK3308 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: CRU should be "rockchip,rk3308-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing, pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "mclk_i2sx_xch_in" - external I2S or SPDIF clock - optional,
- "mac_clkin" - external MAC clock - optional
Example: Clock controller node:
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: serial@ff0a0000 {
compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
reg = <0x0 0xff0a0000 0x0 0x100>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};

72
Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml Normal file
View File

@@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip rk3506 Family Clock and Reset Control Module
maintainers:
- Finley Xiao <finley.xiao@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
The RK3506 clock controller generates the clock and also implements a reset
controller for SoC peripherals. For example it provides SCLK_UART2 and
PCLK_UART2, as well as SRST_P_UART2 and SRST_UART2 for the second UART
module.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clock and reset IDs
are defined as preprocessor macros in dt-binding headers.
properties:
compatible:
enum:
- rockchip,rk3506-cru
- rockchip,rk3506-grf-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: xin24m
- const: xin32k
assigned-clocks: true
assigned-clock-rates: true
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description: >
phandle to the syscon managing the "general register files". It is used
for GRF muxes, if missing any muxes present in the GRF will not be
available.
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
cru: clock-controller@ff9a0000 {
compatible = "rockchip,rk3506-cru";
reg = <0xff9a0000 0x20000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

66
Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.txt Normal file
View File

@@ -0,0 +1,66 @@
* Rockchip RK3568 Clock and Reset Unit
The RK3568 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: PMU for CRU should be "rockchip,rk3568-pmucru"
- compatible: CRU should be "rockchip,rk3568-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing, pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "i2sx_mclkin" - external I2S clock - optional,
- "xin_osc0_usbphyx_g" - external USBPHY clock - optional,
- "xin_osc0_mipidsiphyx_g" - external MIPIDSIPHY clock - optional,
Example: Clock controller node:
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rK3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
cru: clock-controller@fdd20000 {
compatible = "rockchip,rK3568-cru";
reg = <0x0 0xfdd20000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart1: serial@fe650000 {
compatible = "rockchip,rK3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe650000 0x0 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
};

63
Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml Normal file
View File

@@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROCKCHIP rk3576 Family Clock Control Module Binding
maintainers:
- Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
The RK3576 clock controller generates the clock and also implements a
reset controller for SoC peripherals.
(examples: provide SCLK_UART2\PCLK_UART2 and SRST_P_UART2\SRST_S_UART2 for UART module)
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3576-cru.h headers and can be
used in device tree sources.
properties:
compatible:
enum:
- rockchip,rk3576-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks: true
assigned-clocks:
minItems: 1
assigned-clock-parents:
minItems: 1
assigned-clock-rates:
minItems: 1
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
# Clock Control Module node:
- |
cru: clock-controller@27200000 {
compatible = "rockchip,rk3576-cru";
reg = <0x27200000 0x50000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

29
Documentation/devicetree/bindings/clock/rockchip,rk618-cru.txt Normal file
View File

@@ -0,0 +1,29 @@
Rockchip RK618 Clock and Reset Unit
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties :
- compatible : Should be "rockchip,rk618-cru"
- clocks : Should contain phandle and clock specifiers for the input clock:
the AP I2S master clock output(mclk) "clkin", and the AP LCDC master
dclk output(dclk) "lcdc0_dclkp".
- #clock-cells : Should be 1.
Example:
&rk618 {
CRU: cru {
compatible = "rockchip,rk618-cru";
clocks = <&cru SCLK_I2S_8CH_OUT>, <&cru DCLK_VOP>;
clock-names = "clkin", "lcdc0_dclkp";
assigned-clocks = <&CRU SCALER_PLLIN_CLK>, <&CRU VIF_PLLIN_CLK>,
<&CRU HDMI_CLK>, <&CRU SCALER_CLK>,
<&CRU CODEC_CLK>;
assigned-clock-parents = <&CRU LCDC0_CLK>, <&CRU LCDC0_CLK>,
<&CRU VIF0_CLK>, <&CRU SCALER_PLL_CLK>,
<&cru SCLK_I2S_8CH_OUT>;
#clock-cells = <1>;
status = "okay";
};
};

63
Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml Normal file
View File

@@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROCKCHIP rv1106 Family Clock Control Module Binding
maintainers:
- Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
The RV1106 clock controller generates the clock and also implements a
reset controller for SoC peripherals.
(examples: provide SCLK_UART2\PCLK_UART2 and SRST_P_UART2\SRST_S_UART2 for UART module)
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rv1106-cru.h headers and can be
used in device tree sources.
properties:
compatible:
enum:
- rockchip,rv1106-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks: true
assigned-clocks:
minItems: 1
assigned-clock-parents:
minItems: 1
assigned-clock-rates:
minItems: 1
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
# Clock Control Module node:
- |
cru: clock-controller@ff3a0000 {
compatible = "rockchip,rv1106-cru";
reg = <0xff3a0000 0x20000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

68
Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.txt Normal file
View File

@@ -0,0 +1,68 @@
* Rockchip RV1126 Clock and Reset Unit
The RV1126 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: PMU for CRU should be "rockchip,rv1126-pmucru"
- compatible: CRU should be "rockchip,rv1126-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing, pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rv1126-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "i2s8ch_mclkin" - external I2S clock - optional,
- "i2s2ch0_mclkin" - external I2S clock - optional,
- "i2s2ch1_mclkin" - external I2S clock - optional,
- "clk_gmac_rgmii_clkin_m0" - external GMAC clock - optional
- "clk_gmac_rgmii_clkin_m1" - external GMAC clock - optional
Example: Clock controller node:
pmucru: clock-controller@ff480000 {
compatible = "rockchip,rv1126-pmucru";
reg = <0x0 0xff480000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
cru: clock-controller@ff490000 {
compatible = "rockchip,rv1126-cru";
reg = <0x0 0xff490000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: serial@ff560000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff560000 0x100>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
};

6
Documentation/devicetree/bindings/connector/usb-connector.yaml
View File

@@ -117,6 +117,12 @@ properties:
description: Set this property if the Type-C connector has no power delivery support.
type: boolean
pd-revision:
description: Set the maximum PD revision of Type-C controller can support,
the descriptors are compliant in binary-coded decimal (i.e. 2.0 is 0200H
and 3.1 is 0310H).
$ref: /schemas/types.yaml#/definitions/uint32
# The following are optional properties for "usb-c-connector" with power
# delivery support.
source-pdos:

11
Documentation/devicetree/bindings/cpufreq/cpufreq-rockchip.txt Normal file
View File

@@ -0,0 +1,11 @@
Binding for Rockchip's CPUFreq driver
===============================
Rockchip's CPUFreq driver attempts to read leakage value from eFuse
and get frequency count from pvtm, then supplies the OPP framework
with 'prop' information which is used to determine opp-microvolt-<name>
property of OPPS when it is parsed by the OPP framework. This is based
on operating-points-v2, but the driver can also create the "cpufreq-dt"
platform_device to compatibility with operating-points.
For more information about the expected DT format [See: ../opp/rockchip-opp.txt].

20
Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
View File

@@ -1,8 +1,24 @@
* Rockchip rk3399 DFI device
* Rockchip DFI device
Required properties:
- compatible: Must be "rockchip,rk3399-dfi".
- compatible: Should be one of the following.
- "rockchip,px30-dfi" - for PX30 SoCs.
- "rockchip,rk1808-dfi" - for RK1808 SoCs.
- "rockchip,rk3128-dfi" - for RK3128 SoCs.
- "rockchip,rk3288-dfi" - for RK3288 SoCs.
- "rockchip,rk3328-dfi" - for RK3328 SoCs.
- "rockchip,rk3368-dfi" - for RK3368 SoCs.
- "rockchip,rk3399-dfi" - for RK3399 SoCs.
- "rockchip,rk3528-dfi" - for RK3528 SoCs.
- "rockchip,rk3562-dfi" - for RK3562 SoCs.
- "rockchip,rk3568-dfi" - for RK3568 SoCs.
- "rockchip,rv1126-dfi" - for RV1126 SoCs.
Required properties for RK3368:
- rockchip,grf: phandle to the syscon managing the "general register files"
Required properties for RK3399:
- reg: physical base address of each DFI and length of memory mapped region
- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
- clocks: phandles for clock specified in "clock-names" property

24
Documentation/devicetree/bindings/devfreq/event/rockchip-nocp.txt Normal file
View File

@@ -0,0 +1,24 @@
* Rockchip NoC (Network on Chip) Probe device
The Rockchip SoCs have NoC (Network on Chip) Probe for NoC bus.
NoC provides the primitive values to get the performance data, The
packets that the Network on Chip (NoC) probes detects are transported
over the network infrastructure to observer units. For example, RK3399
has multiple NoC probes to monitor traffic statistics for analyzing the
transaction flow.
Required properties:
- compatible: Should be one of the following.
- "rockchip,rk3288-nocp" - for RK3288 SoC.
- "rockchip,rk3368-nocp" - for RK3368 SoC.
- "rockchip,rk3399-nocp" - for RK3399 SoC.
- "rockchip,rk3568-nocp" - for RK3568 SoC.
- reg: physical base address of each NoC Probe and length of memory mapped region.
Example : NoC Probe nodes in Device Tree are listed below.
nocp_cci_msch0: nocp-cci-msch0@ffa86000 {
compatible = "rockchip,rk3399-nocp";
reg = <0xffa86000 0x400>;
};

120
Documentation/devicetree/bindings/devfreq/rockchip_dmc.txt Normal file
View File

@@ -0,0 +1,120 @@
* Rockchip DMC(Dynamic Memory Controller) device
Required properties:
- compatible: Should be one of the following.
- "rockchip,px30-dmc" - for PX30 SoCs.
- "rockchip,rk1808-dmc" - for RK1808 SoCs.
- "rockchip,rk3128-dmc" - for RK3128 SoCs.
- "rockchip,rk3228-dmc" - for RK3228 SoCs.
- "rockchip,rk3288-dmc" - for RK3288 SoCs.
- "rockchip,rk3308-dmc" - for RK3308 SoCs.
- "rockchip,rk3328-dmc" - for RK3328 SoCs.
- "rockchip,rk3399-dmc" - for RK3399 SoCs.
- "rockchip,rk3528-dmc" - for RK3528 SoCs.
- "rockchip,rk3562-dmc" - for RK3562 SoCs.
- "rockchip,rk3568-dmc" - for RK3568 SoCs.
- "rockchip,rk3588-dmc" - for RK3588 SoCs.
- "rockchip,rv1126-dmc" - for RV1126 SoCs.
- devfreq-events: Node to get DDR loading, Refer to
Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt
- interrupts: The interrupt number to the CPU. The interrupt specifier format
depends on the interrupt controller. It should be DCF interrupts,
when DDR dvfs finish, it will happen.
- clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon";
- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
Optional properties:
- ddr_timing: DDR timing need to pass to arm trust firmware
- upthreshold: The upthreshold to simpleondeamnd policy
- downdifferential: The downdifferential to simpleondeamnd policy
- vop-bw-dmc-freq: The property is an array of 3-tuples items, and
each item consists of bandwidth and frequency like
<min-bandwidth max-bandwidth frequency>.
min-bandwidth: minimum ddr bandwidth in Mbyte/sec.
max-bandwidth: maximum ddr bandwidth in Mbyte/sec.
frequency: ddr frequency in KHz.
- #cooling-cells: This property indicates dmc can work as a cooling device
- ddr_power_model: Sets power model parameters.
- dynamic-power-coefficient: A u32 value that represents the running time dynamic
power coefficient in units of mW/MHz/uVolt^2. The coefficient can either be
calculated from power measurements or derived by analysis.
- static-power-coefficient: A u32 value that represents the static power
coefficient.
- ts: An array containing coefficients for the temperature scaling factor.
Used as : tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0], where T = temperature
- thermal-zone: A string identifying the thermal zone used for the dmc
Example:
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <21>;
pd_idle = <0>;
sr_idle = <0>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
dram_dll_dis_freq = <300>;
phy_dll_dis_freq = <125>;
ddr3_odt_dis_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
phy_ddr3_odt = <PHY_DRV_ODT_240>;
lpddr3_odt_dis_freq = <333>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
phy_lpddr3_odt = <PHY_DRV_ODT_240>;
lpddr4_odt_dis_freq = <333>;
lpddr4_drv = <LP4_PDDS_60ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_odt = <PHY_DRV_ODT_60>;
};
dmc_opp_table: dmc_opp_table {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <900000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <900000>;
};
};
dmc: dmc {
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
ddr_timing = <&ddr_timing>;
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
upthreshold = <15>;
downdifferential = <10>;
#cooling-cells = <2>;
ddr_power_model: ddr_power_model {
dynamic-power-coefficient = <120>;
static-power-coefficient = <300>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
}
status = "disabled";
};

49
Documentation/devicetree/bindings/display/bridge/adi,adv7125.txt Normal file
View File

@@ -0,0 +1,49 @@
Analog Device ADV7125 RGB to VGA DAC bridge
-------------------------------
The ADV7125 is a digital-to-analog converter that outputs VGA signals from a
RGB input.
Required properties:
- compatible: Should be "adi,adv7125"
Optional properties:
- psave-gpios: Power save control GPIO
Required nodes:
The ADV7125 has two video ports. Their connections are modeled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
- Video port 0 for RGB input
- Video port 1 for VGA output
Example
-------
adv7125: encoder@0 {
compatible = "adi,adv7125";
#address-cells = <1>;
#size-cells = <0>;
ports {
port@0 {
reg = <0>;
adv7125_in: endpoint@0 {
remote-endpoint = <&rgb_out>;
};
};
port@1 {
reg = <1>;
adv7125_out: endpoint@0 {
remote-endpoint = <&vga_connector_in>;
};
};
};
};

39
Documentation/devicetree/bindings/display/bridge/anx6345.txt Normal file
View File

@@ -0,0 +1,39 @@
Analogix ANX6345 eDP Transmitter
--------------------------------
The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
portable devices.
Required properties:
- compatible : "analogix,anx6345"
- reg : I2C address of the device
- reset-gpios : Which GPIO to use for reset
Optional properties:
- dvdd12-supply : Regulator for 1.2V digital core power.
- dvdd25-supply : Regulator for 2.5V digital core power.
- panel-supply : Regulator for the power of the panel.
- edid : verbatim EDID data block describing attached
panel, only used when the panel has no EDID info.
- Video port for RGB input, using the DT bindings defined in [1].
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
anx6345: anx6345@38 {
compatible = "analogix,anx6345";
reg = <0x38>;
reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
panel-supply = <&reg_dc1sw>;
dvdd25-supply = <&reg_dldo2>;
dvdd12-supply = <&reg_fldo1>;
port {
anx6345_in: endpoint {
remote-endpoint = <&tcon0_out_anx6345>;
};
};
};

15
Documentation/devicetree/bindings/display/bridge/dw-hdmi-hdcp2.txt Normal file
View File

@@ -0,0 +1,15 @@
Device-Tree bindings for dw hdmi hdcp2
Required properties:
- compatible : Should be "rockchip,rk3399-hdmi-hdcp2".
Example:
hdmi_hdcp2: hdmi-hdcp2@ff988000 {
compatible = "rockchip,rk3399-hdmi-hdcp2";
reg = <0x0 0xff988000 0x0 0x2000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_HDCP22>, <&cru PCLK_HDCP22>,
<&cru HCLK_HDCP22>;
clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi";
status = "disabled";
};

48
Documentation/devicetree/bindings/display/bridge/rk1000.txt Normal file
View File

@@ -0,0 +1,48 @@
Rockchip RK1000 TVEncoder
-------------------------------
The RK1000-TVE are RK1000 TV Encoder register block.
The chip is connected to an i2c bus.
Required properties:
- compatible: should be "rockchip,rk1000-tve"
- reg: I2C slave address
- rockchip,data-width: should be <18> or <24>
- rockchip,output: This describes the output face
- rockchip,ctl: phandle to the rk1000 core controller
Optional properties:
- rockchip,tvemode: tve preferred mode, 0 for PAL, 1 for NTSC
Required node:
The rk1000 tve has one video port. its connection is modeled using the OF
graph binding specified in Documentation/devicetree/bindings/graph.txt.
- Video port 0 for LVDS input
Example
-------
rk1000-tve@42 {
status = "okay";
compatible = "rockchip,rk1000-tve";
reg = <0x42>;
rockchip,data-width = <24>;
rockchip,output = "rgb";
rockchip,ctl = <&rk1000_ctl>;
rockchip,tvemode = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tve_in: port@0 {
reg = <0>;
tve_in_lvds: endpoint {
remote-endpoint = <&lvds_out_tve>;
};
};
};
};

159
Documentation/devicetree/bindings/display/bridge/rohm-bu18xl82.txt Normal file
View File

@@ -0,0 +1,159 @@
ROHM BU18TL82/BU18RL82 Clockless Link-BD Serializer/Deserializer bridge bindings
Required properties:
- compatible: "rohm,bu18tl82" or "rohm,bu18rl82"
- reg: i2c address of the bridge
- serdes-init-sequence: register initial code from Rohm vendor
optional properties:
- reset-gpios: a GPIO spec for the reset pin
- enable-gpios: a GPIO spec for the enable pin
- power-supply: Reference to the regulator powering the serdes power supply pins
- sel-mipi: string property for mipi dsi data stream input
Example:
/ {
panel {
compatible = "simple-panel";
backlight = <&backlight>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <87000000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <32>;
hsync-len = <10>;
hback-porch = <22>;
vfront-porch = <10>;
vsync-len = <4>;
vback-porch = <7>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel0_in_i2c2_bu18rl82: endpoint {
remote-endpoint = <&i2c2_bu18rl82_out_panel0>;
};
};
};
};
};
&dsi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_i2c2_bu18tl82: endpoint {
remote-endpoint = <&i2c2_bu18tl82_in_dsi0>;
};
};
};
};
&i2c2 {
status = "okay";
bu18tl82: bu18tl82@10 {
compatible = "rohm,bu18tl82";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&ser0_rst_gpio>;
reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
sel-mipi;
status = "okay";
serdes-init-sequence = [
/* TL82 Pattern Gen Set 1
* Horizontal Gray Scale 256 steps
*/
040A 0010
040B 0080
040C 0080
040D 0080
0444 0019
0445 0020
0446 001f
...
];
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2c2_bu18tl82_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_i2c2_bu18tl82>;
};
};
port@1 {
reg = <1>;
i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint {
remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>;
};
};
};
};
bu18rl82: bu18rl82@30 {
compatible = "rohm,bu18rl82";
reg = <0x30>;
status = "okay";
serdes-init-sequence = [
/* RL82 Pattern Gen Set
* Vertical Gray Scale Color Bar
*/
060A 00B0
060B 00FF
060C 00FF
060D 00FF
0644 0019
0645 0020
0646 001f
...
];
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint {
remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>;
};
};
port@1 {
reg = <1>;
i2c2_bu18rl82_out_panel0: endpoint {
remote-endpoint = <&panel0_in_i2c2_bu18rl82>;
};
};
};
};
};

116
Documentation/devicetree/bindings/display/panel/panel-rgb.txt Normal file
View File

@@ -0,0 +1,116 @@
RGB Display Panel
==================
This describe the panel property rgb-mode for parallel and serial
RGB output interface. rgb-mode should be "p888", "p666", "p565", "s888"
and "s888-dummy", the following describe the connection relations.
p888 mode:
___ ___ ___ ___ ___ ___ ___
dclk __/ \___/ \___/ \___/ \___/ \___/ \___/ \___
______ ______ ______ ______ ______ ______ ______
DATA23 ><__R7__><__R7__><__R7__><__R7__><__R7__><__R7__><__R7__><
DATA22 ><__R6__><__R6__><__R6__><__R6__><__R6__><__R6__><__R6__><
DATA21 ><__R5__><__R5__><__R5__><__R5__><__R5__><__R5__><__R5__><
DATA20 ><__R4__><__R4__><__R4__><__R4__><__R4__><__R4__><__R4__><
DATA19 ><__R3__><__R3__><__R3__><__R3__><__R3__><__R3__><__R3__><
DATA18 ><__R2__><__R2__><__R2__><__R2__><__R2__><__R2__><__R2__><
DATA17 ><__R1__><__R1__><__R1__><__R1__><__R1__><__R1__><__R1__><
DATA16 ><__R0__><__R0__><__R0__><__R0__><__R0__><__R0__><__R0__><
______ ______ ______ ______ ______ ______ ______
DATA15 ><__G7__><__G7__><__G7__><__G7__><__G7__><__G7__><__G7__><
DATA14 ><__G6__><__G6__><__G6__><__G6__><__G6__><__G6__><__G6__><
DATA13 ><__G5__><__G5__><__G5__><__G5__><__G5__><__G5__><__G5__><
DATA12 ><__G4__><__G4__><__G4__><__G4__><__G4__><__G4__><__G4__><
DATA11 ><__G3__><__G3__><__G3__><__G3__><__G3__><__G3__><__G3__><
DATA10 ><__G2__><__G2__><__G2__><__G2__><__G2__><__G2__><__G2__><
DATA9 ><__G1__><__G1__><__G1__><__G1__><__G1__><__G1__><__G1__><
DATA8 ><__G0__><__G0__><__G0__><__G0__><__G0__><__G0__><__G0__><
______ ______ ______ ______ ______ ______ ______
DATA7 ><__B7__><__B7__><__B7__><__B7__><__B7__><__B7__><__B7__><
DATA6 ><__B6__><__B6__><__B6__><__B6__><__B6__><__B6__><__B6__><
DATA5 ><__B5__><__B5__><__B5__><__B5__><__B5__><__B5__><__B5__><
DATA4 ><__B4__><__B4__><__B4__><__B4__><__B4__><__B4__><__B4__><
DATA3 ><__B3__><__B3__><__B3__><__B3__><__B3__><__B3__><__B3__><
DATA2 ><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><
DATA1 ><__B1__><__B1__><__B1__><__B1__><__B1__><__B1__><__B1__><
DATA0 ><__B0__><__B0__><__B0__><__B0__><__B0__><__B0__><__B0__><
pixel | n | n+1 | n+3 | n+4 | n+5 | n+6 | n+7 |
p666 mode:
___ ___ ___ ___ ___ ___ ___
dclk __/ \___/ \___/ \___/ \___/ \___/ \___/ \___
______ ______ ______ ______ ______ ______ ______
DATA17 ><__R5__><__R5__><__R5__><__R5__><__R5__><__R5__><__R5__><
DATA16 ><__R4__><__R4__><__R4__><__R4__><__R4__><__R4__><__R4__><
DATA15 ><__R3__><__R3__><__R3__><__R3__><__R3__><__R3__><__R3__><
DATA14 ><__R2__><__R2__><__R2__><__R2__><__R2__><__R2__><__R2__><
DATA13 ><__R1__><__R1__><__R1__><__R1__><__R1__><__R1__><__R1__><
DATA12 ><__R0__><__R0__><__R0__><__R0__><__R0__><__R0__><__R0__><
______ ______ ______ ______ ______ ______ ______
DATA11 ><__G5__><__G5__><__G5__><__G5__><__G5__><__G5__><__G5__><
DATA10 ><__G4__><__G4__><__G4__><__G4__><__G4__><__G4__><__G4__><
DATA9 ><__G3__><__G3__><__G3__><__G3__><__G3__><__G3__><__G3__><
DATA8 ><__G2__><__G2__><__G2__><__G2__><__G2__><__G2__><__G2__><
DATA7 ><__G1__><__G1__><__G1__><__G1__><__G1__><__G1__><__G1__><
DATA6 ><__G0__><__G0__><__G0__><__G0__><__G0__><__G0__><__G0__><
______ ______ ______ ______ ______ ______ ______
DATA5 ><__B5__><__B5__><__B5__><__B5__><__B5__><__B5__><__B5__><
DATA4 ><__B4__><__B4__><__B4__><__B4__><__B4__><__B4__><__B4__><
DATA3 ><__B3__><__B3__><__B3__><__B3__><__B3__><__B3__><__B3__><
DATA2 ><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><
DATA1 ><__B1__><__B1__><__B1__><__B1__><__B1__><__B1__><__B1__><
DATA0 ><__B0__><__B0__><__B0__><__B0__><__B0__><__B0__><__B0__><
pixel | n | n+1 | n+3 | n+4 | n+5 | n+6 | n+7 |
p565 mode:
___ ___ ___ ___ ___ ___ ___
dclk __/ \___/ \___/ \___/ \___/ \___/ \___/ \___
______ ______ ______ ______ ______ ______ ______
DATA15 ><__R4__><__R4__><__R4__><__R4__><__R4__><__R4__><__R4__><
DATA14 ><__R3__><__R3__><__R3__><__R3__><__R3__><__R3__><__R3__><
DATA13 ><__R2__><__R2__><__R2__><__R2__><__R2__><__R2__><__R2__><
DATA12 ><__R1__><__R1__><__R1__><__R1__><__R1__><__R1__><__R1__><
DATA11 ><__R0__><__R0__><__R0__><__R0__><__R0__><__R0__><__R0__><
______ ______ ______ ______ ______ ______ ______
DATA10 ><__G5__><__G5__><__G5__><__G5__><__G5__><__G5__><__G5__><
DATA9 ><__G4__><__G4__><__G4__><__G4__><__G4__><__G4__><__G4__><
DATA8 ><__G3__><__G3__><__G3__><__G3__><__G3__><__G3__><__G3__><
DATA7 ><__G2__><__G2__><__G2__><__G2__><__G2__><__G2__><__G2__><
DATA6 ><__G1__><__G1__><__G1__><__G1__><__G1__><__G1__><__G1__><
DATA5 ><__G0__><__G0__><__G0__><__G0__><__G0__><__G0__><__G0__><
______ ______ ______ ______ ______ ______ ______
DATA4 ><__B4__><__B4__><__B4__><__B4__><__B4__><__B4__><__B4__><
DATA3 ><__B3__><__B3__><__B3__><__B3__><__B3__><__B3__><__B3__><
DATA2 ><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><
DATA1 ><__B1__><__B1__><__B1__><__B1__><__B1__><__B1__><__B1__><
DATA0 ><__B0__><__B0__><__B0__><__B0__><__B0__><__B0__><__B0__><
pixel | n | n+1 | n+3 | n+4 | n+5 | n+6 | n+7 |
s888 mode:
___ ___ ___ ___ ___ ___ ___
dclk __/ \___/ \___/ \___/ \___/ \___/ \___/ \___
______ ______ ______ ______ ______ ______ ______
DATA7 ><__R7__><__G7__><__B7__><__R7__><__G7__><__B7__><__R7__><
DATA6 ><__R6__><__G6__><__B6__><__R6__><__G6__><__B6__><__R6__><
DATA5 ><__R5__><__G5__><__B5__><__R5__><__G5__><__B5__><__R5__><
DATA4 ><__R4__><__G4__><__B4__><__R4__><__G4__><__B4__><__R4__><
DATA3 ><__R3__><__G3__><__B3__><__R3__><__G3__><__B3__><__R3__><
DATA2 ><__R2__><__G2__><__B2__><__R2__><__G2__><__B2__><__R2__><
DATA1 ><__R1__><__G1__><__B1__><__R1__><__G1__><__B1__><__R1__><
DATA0 ><__R0__><__G0__><__B0__><__R0__><__G0__><__B0__><__R0__><
pixel | --------- n --------- | ------- n + 1 ------- | --------
s888-dummy mode:
___ ___ ___ ___ ___ ___ ___ ___
dclk __/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \___
______ ______ ______ ______ ______ ______ ______ ______
DATA7 ><__R7__><__G7__><__B7__><_NULL_><__R7__><__G7__><__B7__><_NULL_><
DATA6 ><__R6__><__G6__><__B6__><_NULL_><__R6__><__G6__><__B6__><_NULL_><
DATA5 ><__R5__><__G5__><__B5__><_NULL_><__R5__><__G5__><__B5__><_NULL_><
DATA4 ><__R4__><__G4__><__B4__><_NULL_><__R4__><__G4__><__B4__><_NULL_><
DATA3 ><__R3__><__G3__><__B3__><_NULL_><__R3__><__G3__><__B3__><_NULL_><
DATA2 ><__R2__><__G2__><__B2__><_NULL_><__R2__><__G2__><__B2__><_NULL_><
DATA1 ><__R1__><__G1__><__B1__><_NULL_><__R1__><__G1__><__B1__><_NULL_><
DATA0 ><__R0__><__G0__><__B0__><_NULL_><__R0__><__G0__><__B0__><_NULL_><
pixel | ------------- n ------------- | ----------- n + 1 ----------- |

74
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
View File

@@ -29,6 +29,10 @@ properties:
# compatible must be listed in alphabetical order, ordered by compatible.
# The description in the comment is mandatory for each compatible.
# common simple panel
- simple-panel
# common simple dsi panel
- simple-panel-dsi
# Ampire AM-1280800N3TZQW-T00H 10.1" WQVGA TFT LCD panel
- ampire,am-1280800n3tzqw-t00h
# Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
@@ -358,6 +362,76 @@ properties:
no-hpd: true
hpd-gpios: true
reset-gpios:
description: GPIO pin to reset the panel
prepare-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
become ready and start receiving video data
enable-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
display the first valid frame after starting to receive
video data
disable-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
turn the display off (no content is visible)
unprepare-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel
to power itself down completely
reset-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
reset itself completely
init-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
send init command sequence after reset deassert
width-mm:
description: width (in millimeters) of the panel's active display area
height-mm:
description: height (in millimeters) of the panel's active display area
bpc:
description: bits per color/component
bus-format:
description: pixel data format on the wire
dsi,lanes:
description: number of active data lanes
dsi,format:
description: pixel format for video mode
dsi,flags:
description: DSI operation mode related flags
panel-init-sequence: true
panel-exit-sequence:
description: |
A byte stream formed by simple multiple dcs packets.
byte 0 - dcs data type
byte 1 - wait number of specified ms after dcs command transmitted
byte 2 - packet payload length
byte 3 - and beyond: number byte of payload
rockchip,cmd-type:
description: default is DSI cmd, or "spi", "mcu" cmd type
spi-sdi:
description: spi init panel for spi-sdi io
spi-scl:
description: spi init panel for spi-scl io
spi-cs:
description: spi init pael for spi-cs io
power-invert:
description: power invert control
vsp-supply:
description: positive voltage supply
vsn-supply:
description: negative voltage supply
additionalProperties: false
required:

7
Documentation/devicetree/bindings/display/rockchip/inno_hdmi-rockchip.txt
View File

@@ -4,10 +4,11 @@ Rockchip specific extensions to the Innosilicon HDMI
Required properties:
- compatible:
"rockchip,rk3036-inno-hdmi";
"rockchip,rk3128-inno-hdmi";
- reg:
Physical base address and length of the controller's registers.
- clocks, clock-names:
Phandle to hdmi controller clock, name should be "pclk"
Phandle to hdmi controller clock, name should be "aclk" and "pclk".
- interrupts:
HDMI interrupt number
- ports:
@@ -21,8 +22,8 @@ hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
clocks = <&cru ACLK_VIO>, <&cru PCLK_HDMI>;
clock-names = "aclk", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;

222
Documentation/devicetree/bindings/display/rockchip/mcu-panel.yaml Normal file
View File

@@ -0,0 +1,222 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/mcu-panel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip MCU Panel
maintainers:
- Damon Ding <damon.ding@rock-chips.com>
allOf:
- $ref: panel-common.yaml#
properties:
bus-format:
description: pixel data format on the wire
backlight: true
enable-gpios:
description: GPIO pin to enable the panel
reset-gpios:
description: GPIO pin to reset the panel
te-gpios:
description: GPIO pin for the soft TE mode
prepare-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
become ready and start receiving video data
enable-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
display the first valid frame after starting to receive
video data
disable-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
turn the display off (no content is visible)
unprepare-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel
to power itself down completely
reset-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
reset itself completely
init-delay-ms:
description: |
the time (in milliseconds) that it takes for the panel to
send init command sequence after reset deassert
width-mm:
description: width (in millimeters) of the panel's active display area
height-mm:
description: height (in millimeters) of the panel's active display area
panel-init-sequence:
description: |
A byte stream formed by init commands.
byte 0 - mcu data type
byte 1 - wait number of specified ms after mcu command transmitted
byte 2 - packet payload length
byte 3 - and beyond: number byte of payload
panel-exit-sequence:
description: A byte stream formed by deinit commands.
panel-frame-sequence:
description: |
A byte stream formed by interframe commands.
display-timings:
description:
Some display panels support several resolutions with different timings.
The display-timings bindings supports specifying several timings and
optionally specifying which is the native mode.
$ref: display-timings.yaml#
port:
$ref: /schemas/graph.yaml#/properties/port
additionalProperties: false
required:
- bus-format
- backlight
- enable-gpios
- reset-gpios
- panel-init-sequence
- panel-exit-sequence
- display-timings
- port
examples:
- |
#include <dt-bindings/display/media-bus-format.h>
&rgb {
mcu_panel: mcu-panel {
bus-format = <MEDIA_BUS_FMT_RGB565_1X16>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
panel-init-sequence = [
00 00 01 e0
01 00 01 00
01 00 01 07
01 00 01 0f
01 00 01 0d
01 00 01 1b
01 00 01 0a
01 00 01 3c
01 00 01 78
01 00 01 4a
01 00 01 07
01 00 01 0e
01 00 01 09
01 00 01 1b
01 00 01 1e
01 00 01 0f
00 00 01 e1
01 00 01 00
01 00 01 22
01 00 01 24
01 00 01 06
01 00 01 12
01 00 01 07
01 00 01 36
01 00 01 47
01 00 01 47
01 00 01 06
01 00 01 0a
01 00 01 07
01 00 01 30
01 00 01 37
01 00 01 0f
00 00 01 c0
01 00 01 10
01 00 01 10
00 00 01 c1
01 00 01 41
00 00 01 c5
01 00 01 00
01 00 01 22
01 00 01 80
00 00 01 36
01 00 01 48
00 00 01 3a
01 00 01 55
00 00 01 b0
01 00 01 00
00 00 01 b1
01 00 01 a0
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6
01 00 01 02
01 00 01 02
00 00 01 b7
01 00 01 c6
00 00 01 be
01 00 01 00
01 00 01 04
00 00 01 e9
01 00 01 00
00 00 01 f7
01 00 01 a9
01 00 01 51
01 00 01 2c
01 00 01 82
00 78 01 11
00 32 01 29
00 00 01 2c
];
panel-exit-sequence = [
00 0a 01 28
00 78 01 10
];
display-timings {
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
clock-frequency = <10453500>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
hfront-porch = <5>;
vback-porch = <10>;
vfront-porch = <5>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
port {
panel_in_rgb: endpoint {
remote-endpoint = <&rgb_out_panel>;
};
};
};
};

312
Documentation/devicetree/bindings/display/rockchip/rockchip,rk618.txt Normal file
View File

@@ -0,0 +1,312 @@
Rockchip RK618 display bridge bindings
======================================
VIF Module
----------
Required properties:
- compatible: value should be one of the following:
"rockchip,rk618-vif"
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
See ../clocks/clock-bindings.txt for details.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "vif", "vif_pre".
Required nodes:
The connections to the video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.
Example:
&rk618 {
status = "okay";
vif {
compatible = "rockchip,rk618-vif";
clocks = <&CRU VIF0_CLK>, <&CRU VIF0_PRE_CLK>;
clock-names = "vif", "vif_pre";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input_rgb: endpoint {
remote-endpoint = <&rgb_out_bridge>;
};
};
port@1 {
reg = <1>;
vif_output_hdmi: endpoint {
remote-endpoint = <&hdmi_input_vif>;
};
};
};
};
};
SCALER Module
----------
Required properties:
- compatible: value should be one of the following:
"rockchip,rk618-scaler"
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
See ../clocks/clock-bindings.txt for details.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "scaler", "vif", "dither".
Required nodes:
The connections to the video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.
Example:
&rk618 {
status = "okay";
scaler {
compatible = "rockchip,rk618-scaler";
clocks = <&CRU SCALER_CLK>, <&CRU DITHER_CLK>, <&CRU VIF0_CLK>;
clock-names = "scaler", "dither", "vif";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
scaler_input_hdmi: endpoint {
remote-endpoint = <&hdmi_output_scaler>;
};
};
port@1 {
reg = <1>;
scaler_output_lvds: endpoint {
remote-endpoint = <&lvds_input_scaler>;
};
};
};
};
};
LVDS Connector
------------
Required properties:
- compatible: value should be one of the following:
"rockchip,rk618-lvds"
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
See ../clocks/clock-bindings.txt for details.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "lvds".
Optional properties:
- dual-channel: boolean. if it exists, enable dual channel mode
Required nodes:
The connections to the video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.
Example:
&rk618 {
status = "okay";
lvds {
compatible = "rockchip,rk618-lvds";
clocks = <&CRU LVDS_CLK>;
clock-names = "lvds";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input_rgb: endpoint {
remote-endpoint = <&rgb_out_bridge>;
};
};
port@1 {
reg = <1>;
lvds_output_panel: endpoint {
remote-endpoint = <&panel_input_lvds>;
};
};
};
};
};
RGB Connector
------------
Required properties:
- compatible: value should be one of the following:
"rockchip,rk618-rgb"
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
See ../clocks/clock-bindings.txt for details.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "rgb".
Required nodes:
The connections to the video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.
Example:
&rk618 {
status = "okay";
rgb {
compatible = "rockchip,rk618-rgb";
clocks = <&CRU RGB_CLK>;
clock-names = "rgb";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input_rgb: endpoint {
remote-endpoint = <&rgb_out_bridge>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
rgb_output_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input_rgb>;
};
};
};
};
};
HDMI Connector
------------
Required properties:
- compatible: value should be one of the following:
"rockchip,rk618-hdmi"
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
See ../clocks/clock-bindings.txt for details.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "hdmi".
- interrupt-parent: phandle for the interrupt gpio controller
- interrupts: GPIO interrupt to which the chip is connected
Required nodes:
The connections to the video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.
Example:
&rk618 {
status = "okay";
hdmi {
compatible = "rockchip,rk618-hdmi";
clocks = <&CRU HDMI_CLK>;
clock-names = "hdmi";
interrupt-parent = <&gpio3>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input_rgb: endpoint {
remote-endpoint = <&rgb_out_bridge>;
};
};
};
};
};
DSI Connector
------------
Required properties:
- compatible: value should be one of the following:
"rockchip,rk618-dsi"
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
See ../clocks/clock-bindings.txt for details.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "dsi".
- #address-cells, #size-cells: should be set respectively to <1> and <0>.
Optional properties:
- rockchip,lane-rate: specifies the lane data rate [Mbps]
Child nodes:
Should contain DSI peripheral nodes
(see Documentation/devicetree/bindings/display/mipi-dsi-bus.txt).
Required nodes:
The connections to the video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.
Example:
&rk618 {
status = "okay";
dsi {
compatible = "rockchip,rk618-dsi";
clocks = <&CRU MIPI_CLK>;
clock-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input_rgb: endpoint {
remote-endpoint = <&rgb_out_bridge>;
};
};
};
};
};

26
Documentation/devicetree/bindings/display/rockchip/rockchip,virtual-connector.txt Normal file
View File

@@ -0,0 +1,26 @@
Rockchip virtual connector driver
================================
Required properties:
- compatible: should be "rockchip,virtual-connector"
patternProperties:
"connector-enable": if this connector should be enabled
"connector-vp-id": which video port this connector attached to.
The connector here should be hdmi0/1, dp0/1, mipi0/1
"virtual-connector-count": the number of virtual connector devices.
"virtualX-disconnected": Set specified virtual connector to disconnected.
The X here should be less than virtual-connector-count.
Example:
vconn {
compatible = "rockchip,virtual-connector";
hdmi0-enable;
hdmi1-enable;
hdmi0-vp-id = <0>;
hdmi1-vp-id = <1>;
virtual-connector-count = <2>;
virtual1-disconnected;
status = "okay";
};

29
Documentation/devicetree/bindings/display/rockchip/rockchip-backlight.txt Normal file
View File

@@ -0,0 +1,29 @@
Rockchip DRM backlight device
================================
Rockchip display controller(see VOP bindings[0]) support CABC function,
and the CABC function required using VOP self pwm to control backlight,
This backlight device manager the backlight PWM, auto select correct
PWM for backlight.
Required properties:
- compatible: Should be "rockchip,drm-backlight"
Other properties are same to commom PWM backlight bindings[1].
[0]: Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
[1]: Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
example:
backlight {
compatible = "rockchip,drm-backlight";
pwms = <&pwm 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <&vdd_bl_reg>;
enable-gpios = <&gpio 58 0>;
};

95
Documentation/devicetree/bindings/display/rockchip/rockchip-eink-panel.txt Normal file
View File

@@ -0,0 +1,95 @@
Rockchip EINK panel
================================
EINK panel timing:
│ │FBL+FSL
│ │
│ │
LBL+LSL│ LDL │ LEL
─────┼────────────────────────────┼───────
│ │
│ │
│ Active Area │FDL
│ │
│ │
─────┼────────────────────────────┼───────
│ │
│ │FEL
│ │
│ │
┌─────────────────────────────────────────────┐
│ Active Area │
│ ┌────────────────────────────┐ │
│ │ │ │
│ │ │ │
│ │ Visible Area │height │vir_height
│ │ │ │
│ │ │ │
│ └────────────────────────────┘ │
│ vidth │
└─────────────────────────────────────────────┘
vir_width
----
Required properties:
- panel,width: visible width of panel in pixels
- panel,height: visible height of panel in pixels
- panel,vir_width: virtual width of panel pixels
- panel,vir_height: virtual height of panel pixels
- panel,sdck: frequency of sdclk in Hz
- panel,lsl: line start length
- panel,lbl: line back porch length
- panel,ldl: line data length
- panel,lel: line end porch length
- panel,gdck-sta: gdck-sta length
- panel,lgonl: lgonl length
- panel,fsl: frame start length
- panel,fbl: frame back porch length
- panel,fdl: frame data length
- panel,fel: frame end porch length
- panel,panel_16bit: 1 for 16bit panel, 0 for 8bit panel
- panel,panel_color: 1 for color panel, 0 for normal panel
- panel,mirror: line scan direction. 0 for from left to right,
1 for from right to left.
- panel,rearrange: image data need special arrangement.
1 for special arrangement, 0 for no arrangement.
- panel,width-mm: physical width of panel in millimeters
- panel,height-mm: physical height of panel in millimeters
Optional properties:
- panel,sdoe_mode: SDOE signal mode setting.
Set to 1, SDOE is active during total horizon.
Set to 0, SDOE is active during total vertical.
If not set, the default value is 0.
- panel,sdce_width: width of SDCE signal.
If not set, the default value is same as "panel,ldl".
- panel,disable_logo: disable show logo. 1 for disable logo, 0 for enable logo.
If not set, the default value is 0.
Example:
&ebc_dev {
/* ED103TC2 panel */
panel,width = <1872>;
panel,height = <1404>;
panel,vir_width = <1872>;
panel,vir_height = <1404>;
panel,sdck = <34000000>;
panel,lsl = <18>;
panel,lbl = <17>;
panel,ldl = <234>;
panel,lel = <7>;
panel,gdck-sta = <34>;
panel,lgonl = <192>;
panel,fsl = <1>;
panel,fbl = <4>;
panel,fdl = <1404>;
panel,fel = <12>;
panel,mirror = <1>;
panel,panel_16bit = <1>;
panel,panel_color = <0>;
panel,width-mm = <157>;
panel,height-mm = <210>;
};

93
Documentation/devicetree/bindings/display/rockchip/rockchip-rgb.yaml Normal file
View File

@@ -0,0 +1,93 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip-rgb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RGB interface
maintainers:
- Sandy Huang <hjc@rock-chips.com>
- Damon Ding <damon.ding@rock-chips.com>
properties:
compatible:
enum:
- rockchip,px30-rgb
- rockchip,rk1808-rgb
- rockchip,rk3066-rgb
- rockchip,rk3128-rgb
- rockchip,rk3288-rgb
- rockchip,rk3308-rgb
- rockchip,rk3368-rgb
- rockchip,rk3506-rgb
- rockchip,rk3562-rgb
- rockchip,rk3568-rgb
- rockchip,rk3588-rgb
- rockchip,rv1106-rgb
- rockchip,rv1108-rgb
- rockchip,rv1126-rgb
phys:
description: phandle for the PHY device
phy-names:
description: should be "phy"
pinctrl-names:
description: the pin control state names; should contain "default"
pinctrl-0:
description: the default pinctrl state (active)
pinctrl-1:
description: the "sleep" pinctrl state
rockchip,data-sync-bypass:
description: bypass the vop data-sync logic from io
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
port for the VOP input
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
port for either a panel or bridge
mcu-panel:
$ref: mcu-panel.yaml#
description:
mcu panel configurations
required:
- compatible
- pinctrl-names
- pinctrl-0
- ports
additionalProperties: false
examples:
- |
rgb: rgb {
compatible = "rockchip,rk3308-rgb";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_ctl>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgb_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_rgb>;
};
};
};
};

46
Documentation/devicetree/bindings/display/rockchip/rockchip_drm_tve.txt Normal file
View File

@@ -0,0 +1,46 @@
Rockchip specific extensions to the TVE
================================
Required properties:
- compatible: "rockchip,rk3328-tve";
- reg: Physical base address and length of the controller's registers.
- ports: contain a port node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt
- rockchip,saturation: the value for TVE_COLOR_BUSRT_SAT(0x78)
- rockchip,brightcontrast: the value for TVE_BRIGHTNESS_CONTRAST(0x90)
- rockchip,adjtiming: the value for TVE_HOR_TIMING3(0x0c)
- rockchip,lumafilter0: the value for TVE_LUMA_FILTER1(0x14)
- rockchip,lumafilter1: the value for TVE_LUMA_FILTER2(0x18)
- rockchip,lumafilter2: the value for TVE_LUMA_FILTER3(0x1c)
- rockchip,daclevel: the value is used to adjust the voltage amplitude of the CVBS
- rockchip,dac1level: only for rv1108 rk322x and rk3328
Optional properties:
- rockchip,tvemode: tve preferred mode, 0 for PAL, 1 for NTSC
Example:
tve: tve@ff373e00 {
compatible = "rockchip,rk3328-tve";
reg = <0x0 0xff373e00 0x0 0x100>,
<0x0 0xff420000 0x0 0x10000>;
rockchip,saturation = <0x00376749>;
rockchip,brightcontrast = <0x0000a305>;
rockchip,adjtiming = <0xb6c00880>;
rockchip,lumafilter0 = <0x01ff0000>;
rockchip,lumafilter1 = <0xf40200fe>;
rockchip,lumafilter2 = <0xf332d70c>;
rockchip,daclevel = <0x22>;
rockchip,dac1level = <0x7>;
rockchip,tvemode = <0>;
status = "disabled";
ports {
tve_in: port {
#address-cells = <1>;
#size-cells = <0>;
tve_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_tve>;
};
};
};
};

56
Documentation/devicetree/bindings/display/rockchip/rockchip_mipi_csi_tx.txt Normal file
View File

@@ -0,0 +1,56 @@
Rockchip MIPI CSI HOST
================================
Required properties:
- compatible: must be one of:
"rockchip,rk1808-mipi-csi".
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
- clocks, clock-names: Phandles to the controller's APB clock(pclk) as
described in [1].
- resets : phandle to the reset of MIPI CSI APB Clock.
- reset-names : should be "apb".
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
Optional properties
- clocks, clock-names:
phandle to the SNPS-PHY config clock, name should be "phy_cfg".
phandle to the SNPS-PHY PLL reference clock, name should be "ref".
phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
phandle to the h2p bridge clock, name should be "h2p".
- phys: phandle to Non-SNPS PHY node
- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
attribute, provides phandle to MIPI PHY node
- rockchip,dual-channel: for dual-channel panel, if not, don't configure
- rockchip,lane-rate: manually configure lane-rate, not necessary.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
[3] Documentation/devicetree/bindings/reset/reset.txt
Example:
For Rockchip RK1808:
csi: csi@ffb20000 {
compatible = "rockchip,rk1808-mipi-csi";
clocks = <&cru PCLK_MIPI_CSI0>, <&mipi_dphy>;
clock-names = "pclk", "hs_clk";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
resets = <&cru SRST_MIPICSI>;
reset-names = "apb";
...
ports {
port {
csi_in_vop: endpoint {
remote-endpoint = <&vop_out_csi>;
};
};
};
};

130
Documentation/devicetree/bindings/dram/rk3399_dram_timing.txt Normal file
View File

@@ -0,0 +1,130 @@
* rk3399 dram default timing is at arch/arm64/boot/dts/rk3399_dram_default_timing.dtsi
Required properties:
- compatible : Should be "rockchip,ddr-timing"
- ddr3_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h.
It select DDR3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected
according to "Speed Bin" in DDR3 datasheet, DO NOT use smaller "Speed Bin" than
DDR3 exactly is.
- pd_idle : Defines the power-down mode auto entry controller clocks.
This parameter defines the number of idle controller clocks that can elapse
before the controller will automatically issue an entry into the appropriate
power-down low power state.
- sr_idle : Defines the Self-Refresh or Self-Refresh with Memory Clock Gating
auto entry periodic cycles.
This parameter defines the number of long count sequences that can elapse
before the controller will automatically issue an entry into the Self-Refresh
or Self-Refresh with Memory Clock Gating low power state.
- sr_mc_gate_idle : Defined the Self-Refresh with Memory and Controller Clock Gating
auto entry periodic cycles.
This parameter defines the number of long count sequences that can elapse before
the controller will automatically issue an entry into the Self-Refresh with
Memory and Controller Clock Gating low power state.
- srpd_lite_idle : Define the Lite Self-Refresh Power-Down auto entry periodic
cycles.
This parameter defines the number of long count sequences that can elapse
before the controller will automatically issue an entry into the
Lite Self-Refresh Power-Down low power state.
- standby_idle : Define the standby mode auto entry periodic cycles.
- auto_lp_dis_freq : It's defined the auto low down mode frequency in MHz (Mega Hz),
when ddr freq greater than or equal this setting value, auto power-down will disable.
- ddr3_dll_dis_freq : It's defined the DDR3 dll bypass frequency in MHz (Mega Hz),
when ddr freq less than or equal this setting value, DDR3 dll will bypssed.
note: if dll was bypassed, the odt also stop working.
- phy_dll_dis_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz),
when ddr freq less than or equal this setting value, phy dll will bypssed.
note: phy dll and phy odt are independent.
- ddr3_odt_dis_freq : Defined the DDR3 odt disable frequency in
MHz (Mega Hz), when ddr frequency less then or equal ethis setting value, the DDR3
ODT are disabled.
- ddr3_drv : Define the driver strength in ohm when connect DDR3.
- ddr3_odt : Define the ODT in ohm when connect DDR3.
- phy_ddr3_ca_drv : Define the PHY CA driver strength in ohm when connect DDR3.
- phy_ddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect DDR3.
- phy_ddr3_odt : Define the phy odt in ohm when connect DDR3.
- lpddr3_odt_dis_freq : Defined the LPDDR3 odt disable frequency in
MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR3
ODT are disabled.
- lpddr3_drv : Define the driver strength in ohm when connect LPDDR3.
- lpddr3_odt : Define the ODT in ohm when connect LPDDR3.
- phy_lpddr3_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR3.
- phy_lpddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR3.
- phy_lpddr3_odt : Define the phy odt in ohm when connect LPDDR3.
- lpddr4_odt_dis_freq : Defined the LPDDR4 odt disable frequency in
MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR4
ODT are disabled.
- lpddr4_drv : Define the driver strength in ohm when connect LPDDR4.
- lpddr4_dq_odt : Define the DQ ODT in ohm when connect LPDDR4.
- lpddr4_ca_odt : Define the CA ODT in ohm when connect LPDDR4.
- phy_lpddr4_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR4.
- phy_lpddr4_ck_cs_drv : Define the PHY CLK and CS driver strength in ohm when connect LPDDR4.
- phy_lpddr4_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR4.
- phy_lpddr4_odt : Define the phy odt in ohm when connect LPDDR4.
Example:
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <21>;
pd_idle = <0>;
sr_idle = <0>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
auto_lp_dis_freq = <666>;
ddr3_dll_dis_freq = <300>;
phy_dll_dis_freq = <260>;
ddr3_odt_dis_freq = <666>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
phy_ddr3_odt = <PHY_DRV_ODT_240>;
lpddr3_odt_dis_freq = <666>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>;
phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>;
phy_lpddr3_odt = <PHY_DRV_ODT_240>;
lpddr4_odt_dis_freq = <933>;
lpddr4_drv = <LP4_PDDS_60ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_odt = <PHY_DRV_ODT_60>;
};
};

80
Documentation/devicetree/bindings/gpio/novo,nca9539-gpio.yaml Normal file
View File

@@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/novo,nca9539-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Novosense I2C GPIO controller
maintainers:
- Cody Xie <cody.xie@rock-chips.com>
description: |
This controller is A GPIO expander with I2C interface and one interrupt pin.
properties:
compatible:
const: novo,nca9539-gpio
reg:
items:
- description: the I2C address containing the GPIO controller registers.
gpio-controller: true
'#gpio-cells':
const: 2
ngpios:
minimum: 0
maximum: 32
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
vdd-supply:
- description: the regulator for the VDD supplier.
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
- vdd-supply
additionalProperties: false
dependencies:
interrupt-controller: [ interrupts ]
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
nca9539_vdd: nca9539-vdd {
compatible = "regulator-fixed";
regulator-name = "nca9539_vdd";
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
};
nca9539_gpio: gpio@74 {
compatible = "novo,nca9539-gpio";
reg = <0x74>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
vdd-supply = <&nca9539_vdd>;
};
...

34
Documentation/devicetree/bindings/hwlock/rockchip-hwspinlock.txt Normal file
View File

@@ -0,0 +1,34 @@
Rockchip HW Spinlock Device Binding
===================================
Required properties :
- compatible : shall contain only one of the following:
"rockchip,hwspinlock"
- reg : the register address of hwspinlock
- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
hwlock, so the number of cells should be <1> here.
- rockchip,hwlock-num-locks ：number of hwlocks provided by this device.
Optional properties :
- rockchip,hwlock-user-id : Set hwlock user id (4 bit, default is 0x01).
Please look at the generic hwlock binding for usage information for consumers,
"Documentation/devicetree/bindings/hwlock/hwlock.txt"
Example of hwlock provider:
hwlock: hwspinlock@ff040000 {
compatible = "rockchip,hwspinlock";
reg = <0 0xff040000 0 0x10000>;
#hwlock-cells = <1>;
rockchip,hwlock-num-locks = <64>;
};
Example of hwlock users:
node {
...
hwlocks = <&hwlock 0>;
...
};

52
Documentation/devicetree/bindings/i3c/rockchip,i3c-master.yaml Normal file
View File

@@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i3c/rockchip,i3c-master.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip I3C master block
allOf:
- $ref: i3c.yaml#
properties:
compatible:
const: rockchip,i3c-master
reg:
maxItems: 1
clocks:
maxItems: 2
clock-names:
minItems: 2
items:
- const: i3c
- const: pclk
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
unevaluatedProperties: false
examples:
- |
i3c0: i3c-master@2abe0000 {
compatible = "rockchip,rk3576-i3c-master";
reg = <0x0 0x2abe0000 0x0 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&cru HCLK_I3C>, <&cru i3C>;
clock-names = "hclk", "i3c";
dmas = <&dmac0 22>, <&dmac0 23>;
dma-names = "rx", "tx";
};

24
Documentation/devicetree/bindings/iio/adc/gpio-muxadc.txt Normal file
View File

@@ -0,0 +1,24 @@
GPIO-controlled Multiplexers (MUX) A/D Converter bindings
Required properties:
- compatible: should be "gpio-muxadc" or others like below
- "sgm3699": for a quad, bidirectional, single-pole/double-throw (SPDT) CMOS analog switch.
- "sgm48752": for a dual, bidirectional, double-pole/double-throw (DPDT) CMOS analog switch.
- io-channels: Channel node of the parent channel that has multiplexed input.
- switch-gpios: Digital control pins to connect the parent adc channel(saradc) to the input adc channel(muxadc).
- labels: The string list for each muxadc channel that should be placed in order.
Example:
muxadc {
compatible = "sgm48752";
io-channels = <&saradc 4>, <&saradc 5>;
switch-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>,
<&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
labels = "wheel_vpropi_r_adc", "wheel_vpropi_l_adc",
"fan_opa_adc", "mid_opa_adc",
"pump_opa_adc", "side_opa_adc",
"dc24vdet_adc", "collision_det_adc_lidar";
pinctrl-names = "default";
pinctrl-0 = <&switch_gpios>;
status = "okay";
};

1
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
View File

@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- rockchip,px30-saradc
- rockchip,rk1808-saradc
- rockchip,rk3308-saradc
- rockchip,rk3328-saradc
- rockchip,rk3568-saradc

69
Documentation/devicetree/bindings/input/rockchip-keys.txt Normal file
View File

@@ -0,0 +1,69 @@
ROCKCHIP ADC attached resistor ladder buttons
------------------------------------
Required properties:
- compatible: "rockchip,key"
- io-channels: Phandle to an ADC channel
Each button (key) is represented as a sub-node of "rockchip,key":
Required subnode-properties:
- label: Descriptive name of the key.
- linux,code: Keycode to emit.
- rockchip,adc_value:: Voltage ADC input when this key is pressed.
Example:
#include <dt-bindings/input/input.h>
rk_key: rockchip-key {
compatible = "rockchip,key";
status = "okay";
io-channels = <&saradc 1>;
vol-up-key {
linux,code = <115>;
label = "volume up";
rockchip,adc_value = <1>;
};
vol-down-key {
linux,code = <114>;
label = "volume down";
rockchip,adc_value = <170>;
};
power-key {
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
label = "power";
gpio-key,wakeup;
};
menu-key {
linux,code = <59>;
label = "menu";
rockchip,adc_value = <355>;
};
home-key {
linux,code = <102>;
label = "home";
rockchip,adc_value = <746>;
};
back-key {
linux,code = <158>;
label = "back";
rockchip,adc_value = <560>;
};
camera-key {
linux,code = <212>;
label = "camera";
rockchip,adc_value = <450>;
};
};

55
Documentation/devicetree/bindings/input/sensors/rk_sensor.txt Normal file
View File

@@ -0,0 +1,55 @@
* Sensor Controller
Required properties:
- compatible: the sensor name,exampel: "gs_mma8452";
- reg: i2c slave address;
- type: sensor type;
- irq-gpio: sensor interrupt gpio pin;
- irq_enable: 1 use irq; 0 use pull mode;
- poll_delay_ms: pull delay time if use pull mode;
- layout: sensor orientation, choose 1-8 to make product work fine;
Example:
hall_sensor: hall-mh248 {
compatible = "hall-mh248";
pinctrl-names = "default";
pinctrl-0 = <&mh248_irq_gpio>;
irq-gpio = <&gpio1 2 IRQ_TYPE_EDGE_RISING>;
hall-active = <1>;
status = "okay";
};
sensor@1d {
compatible = "gs_mma8452";
reg = <0x1d>;
type = <SENSOR_TYPE_ACCEL>;
irq-gpio = <&gpio8 GPIO_A0 IRQ_TYPE_EDGE_FALLING>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
sensor@19 {
compatible = "gs_lis3dh";
reg = <0x19>;
type = <SENSOR_TYPE_ACCEL>;
irq-gpio = <&gpio0 GPIO_A0 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
TYPE:
SENSOR_TYPE_NULL 0
SENSOR_TYPE_ANGLE 1
SENSOR_TYPE_ACCEL 2
SENSOR_TYPE_COMPASS 3
SENSOR_TYPE_GYROSCOPE 4
SENSOR_TYPE_LIGHT 5
SENSOR_TYPE_PROXIMITY 6
SENSOR_TYPE_TEMPERATURE 7
SENSOR_TYPE_PRESSURE 8
SENSOR_TYPE_HALL 9
define SENSOR_NUM_TYPES 10

35
Documentation/devicetree/bindings/input/touchscreen/goodix_gt1x.txt Normal file
View File

@@ -0,0 +1,35 @@
Goodix GT1x series touch controller
Required properties:
- compatible : Should be "goodix,gt1x", compatible with the
of_match_table defined in driver.
- reg : I2C slave address of the device.
- goodix,irq-gpio : Interrupt gpio which is to provide interrupts to
host, same as "interrupts" node.
- goodix,rst-gpio: : Reset gpio to control the reset of chip.
Optional properties:
- power-supply : Power supply needed to power up the device, when use
external regulator, do not add this property.
- goodix,ic_type : Specify touch IC type.
Example:
i2c@00000000 {
/* ... */
gt9xx@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
status = "okay";
goodix,rst-gpio = <&msm_gpio 12 0x0>;
goodix,irq-gpio = <&msm_gpio 13 0x2800>;
goodix,ic_type = "gt5688";
};
/* ... */
};

16
Documentation/devicetree/bindings/iommu/rockchip,rk32-iommu.txt Normal file
View File

@@ -0,0 +1,16 @@
ROCKCHIP rk32 IOMMU H/W
Required properties:
- compatible : "iommu,iep_mmu"
- reg : Should contain address and length for each
of the IOMMU register blocks.
- interrupts : Should contain irq type,irq no,and level type
Example:
iep_mmu {
dbgname = "iep";
compatible = "iommu,iep_mmu";
reg = <0xff900800 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
};

42
Documentation/devicetree/bindings/leds/leds-rgb13h.txt Normal file
View File

@@ -0,0 +1,42 @@
The device is controlled through enable gpio pin.
gpio asserted high, enable flash strobe.
Required properties:
- compatible : Must be "led,rgb13h".
- enable-gpios : Must be device tree identifier of the flash device enable pin.
A discrete LED element connected to the device must be represented by a child
node - see Documentation/devicetree/bindings/leds/common.txt.
Required properties of the LED child node:
- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt
Optional properties of the LED child node:
- label : see Documentation/devicetree/bindings/leds/common.txt
Special properties:
- rockchip,camera-module-index : indicate which camera the flash belongs to.
- rockchip,camera-module-facing : indicate the camera facing.
flash_rgb13h: flash-rgb13h {
compatible = "led,rgb13h";
label = "gpio-flash";
led-max-microamp = <20000>;
flash-max-microamp = <20000>;
flash-max-timeout-us = <1000000>;
enable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
};
&i2c2 {
...
ov2680@10 {
...
flash-leds = <&flash_rgb13h>;
...
};
};

13
Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
View File

@@ -10,6 +10,7 @@ Required properties:
- compatible: should be one of the following.
- "rockchip,rk3368-mbox" for rk3368
- "rockchip,rk3576-mbox" for rk3576
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The interrupt number to the cpu. The interrupt specifier format
@@ -17,6 +18,18 @@ Required properties:
- #mbox-cells: Common mailbox binding property to identify the number
of cells required for the mailbox specifier. Should be 1
Optional properties :
- wakeup-source: Mailbox irq can be used as a wakeup source.
- rockchip,txpoll-period-us: TX Done polling interval in microseconds,
only support when CONFIG_MAILBOX_POLL_PERIOD_US is selected.
- rockchip,txpoll-period-ms: TX Done polling interval in milliseconds.
- rockchip,enable-cmd-trigger: Enable write cmd register to trigger interrupt.
This is only support from rockchip,rk3576-mbox.
- rockchip,txdone-ack: Enable if the mailbox client use ACK to check TX_DONE.
- rockchip,txdone-irq: Enable if the controller can trigger TX_DONE interrupt.
- rockchip,tx-direction-b2a: To specify the TX direction as B2A for local.
Example:
--------

52
Documentation/devicetree/bindings/media/i2c/aw36518.txt Normal file
View File

@@ -0,0 +1,52 @@
* AW36518 flash driver support
Required Properties:
- compatible: Must contain "awinic,aw36518"
- reg: I2C slave address
- enable-gpios: Specifier of the GPIO connected to strobe/torch EN pin
this pin is for hardware flash/torch mode, if not, will using i2c control.
- tx-gpio: Specifier of the GPIO connected to TX pin
this pin is synchronization input for RF power Amplifier Pulse Eventr;
if not, will using assist mode.
A discrete LED element connected to the device must be represented by a child
node - see Documentation/devicetree/bindings/leds/common.txt.
Required properties of the LED child node:
- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt
Special properties:
- rockchip,camera-module-index : indicate which camera the flash belongs to.
- rockchip,camera-module-facing : indicate the camera facing.
Example:
&i2c1 {
...
aw36518: aw36518@63 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "awinic,aw36518";
status = "okay";
reg = <0x63>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
enable-gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
tx-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
aw36518_led0: led@0 {
reg = <0x0>;
led-max-microamp = <386000>;
flash-max-microamp = <1500000>;
flash-max-timeout-us = <1600000>;
};
};
...
ov13850: ov13850@10 {
...
flash-leds = <&aw36518_led0>;
...
};
...
}

74
Documentation/devicetree/bindings/media/i2c/cn3927v.txt Normal file
View File

@@ -0,0 +1,74 @@
* CN3927V vcm driver support
Required Properties:
- compatible: Must contain "chipnext,cn3927v"
- reg: I2C slave address
Common Optional Properties:
- rockchip,vcm-max-current: max output current, default 120, unit: mA.
- rockchip,vcm-start-current: starting current.
- rockchip,vcm-rated-current: rate current.
Normal Mode Optional Properties:
- rockchip,vcm-step-mode: S[3:2]: Codes per step, S[1:0]: Step period, default 0xd.
- rockchip,vcm-edlc-enable: Enhanced Dual Level Control Mode enable, default 0.
- rockchip,vcm-dlc-enable: Dual level control enable, default 0.
- rockchip,vcm-mclk: MCLK[1:0], default 0.
- rockchip,vcm-t-src: T_SRC[4:0], default 0.
Advanced Mode Optional Properties:
- rockchip,vcm-adcanced-mode: Enable Advanced mode, 0: Normal mode; 1: Advanced mode.
- rockchip,vcm-sac-mode: SAC_MODE[3:0]: 0x0~0xe, other reserved.
- rockchip,vcm-sac-time: SACT[6:0]: SAC time selection.
- rockchip,vcm-prescl: PRESC[1:0]: Prescaler (SAC Period Divider).
: SAC setting time = tVIB = (3.81ms+(SACT [6:0]) x 0.03ms)) x (PRESC[1:0]).
NRC(Noise Reduction Control) mode Properties:
Current not used, for future use
- rockchip,vcm-nrc-en: NRC EN: 0:Direct mode, 1:NRC mode.
- rockchip,vcm-nrc-mode: NRC_MODE: 0: NRC start, 1: NRC landing.
- rockchip,vcm-nrc-preset: PRESET[7:0]: NRC Current Setting.
- rockchip,vcm-nrc-infl: NRC_INF[1:0]: NRC inflection point.
- rockchip,vcm-nrc-time: NRC Operation Time: 0: 32ms, 1: 64ms.
Required Special properties:
- rockchip,camera-module-index : indicate which camera the vcm belongs to.
- rockchip,camera-module-facing : indicate the camera facing.
Example:
&i2c1 {
...
cn3927v: cn3927v@c {
compatible = "chipnext,cn3927v";
status = "okay";
reg = <0x0c>;
rockchip,vcm-max-current = <120>;
rockchip,vcm-start-current = <30>;
rockchip,vcm-rated-current = <80>;
rockchip,vcm-step-mode = <0x8>;
rockchip,vcm-edlc-enable = <0>;
rockchip,vcm-dlc-enable = <0>;
rockchip,vcm-mclk = <1>;
rockchip,vcm-t-src = <0>;
rockchip,vcm-adcanced-mode = <1>;
rockchip,vcm-sac-mode = <0x03>;
rockchip,vcm-sac-time = <0x28>;
rockchip,vcm-prescl = <0x02>;
rockchip,vcm-nrc-en = <0>;
rockchip,vcm-nrc-mode = <1>;
rockchip,vcm-nrc-preset = <0x11110000>;
rockchip,vcm-nrc-infl = <0x01>;
rockchip,vcm-nrc-time = <0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
...
s5kjn1: s5kjn1@10 {
...
lens-focus = <&cn3927v>;
...
};
...
}

44
Documentation/devicetree/bindings/media/i2c/dw9800w.txt Normal file
View File

@@ -0,0 +1,44 @@
* DW9800W vcm driver support
Required Properties:
- compatible: Must contain "chipnext,cn3927v"
- reg: I2C slave address
Optional Properties:
- rockchip,vcm-max-current: max output current, unit: mA.
- rockchip,vcm-start-current: starting current.
- rockchip,vcm-rated-current: rate current.
- rockchip,vcm-step-mode: 0 SAC2 mode,1 SAC3 mode,2 SAC4 mode,3 SAC5 mode,4 Direct mode,5 LSC mode.
- rockchip,vcm-t-src : SACT[5:0], Tvib = 6.3ms + SACT[5:0]*0.1ms, recommend: 10ms.
- rockchip,vcm-t-div : 0 Tvibx2(double),1 Tvibx1(default),2 Tvibx1/2(half),3 Tvibx1/4(quarter),4 Tvibx8,5 Tvibx4,
Required Special properties:
- rockchip,camera-module-index : indicate which camera the vcm belongs to.
- rockchip,camera-module-facing : indicate the camera facing.
Example:
&i2c4 {
...
dw9800w: dw9800w@c {
compatible = "dongwoon,dw9800w";
status = "okay";
reg = <0x0c>;
rockchip,vcm-max-current = <100>;
rockchip,vcm-start-current = <20>;
rockchip,vcm-rated-current = <80>;
rockchip,vcm-step-mode = <1>;
rockchip,vcm-t-src = <0x25>;
rockchip,vcm-t-div = <1>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
...
imx586: s5kjn1@1a {
...
lens-focus = <&dw9800w>;
...
};
...
}

44
Documentation/devicetree/bindings/media/i2c/gc2053.txt Normal file
View File

@@ -0,0 +1,44 @@
* galaxycore,gc2053 MIPI sensor
Required Properties:
- compatible: should be "galaxycore,gc2053"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
- pwdn-gpios: Low active power-down gpio
Attention:
GC2053 device address 0x37(7bit)
Example:
&i2c1 {
status = "okay";
gc2053: gc2053@37 {
compatible = "galaxycore,gc2053";
reg = <0x37>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
power-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "YT-RV1109-2-V1";
rockchip,camera-module-lens-name = "40IR-2MP-F20";
port {
ucam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2>;
};
};
};
};

43
Documentation/devicetree/bindings/media/i2c/gc2093.txt Normal file
View File

@@ -0,0 +1,43 @@
* galaxycore,gc2093 MIPI sensor
Required Properties:
- compatible: should be "galaxycore,gc2093"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
- pwdn-gpios: High active power-down gpio
Attention:
GC2093 device address 0x37(7bit)
Example:
&i2c1 {
status = "okay";
gc2093: gc2093@37 {
compatible = "galaxycore,gc2093";
reg = <0x37>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&mipicsi_clk0>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "YT-RV1109-2-V1";
rockchip,camera-module-lens-name = "40IR-2MP-F20";
port {
ucam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2>;
};
};
};
};

44
Documentation/devicetree/bindings/media/i2c/gc4663.txt Normal file
View File

@@ -0,0 +1,44 @@
* galaxycore,gc4663 MIPI sensor
Required Properties:
- compatible: should be "galaxycore,gc4663"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: High active reset gpio
Attention:
GC4C33 device address 0x29(7bit)
Example:
&i2c1 {
status = "okay";
gc4663: gc4663@29 {
compatible = "galaxycore,gc4663";
reg = <0x29>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "TRC-2232A6";
rockchip,camera-module-lens-name = "28IRC-4M-F22";
/* NO_HDR:0 HDR_X2:5 HDR_X3:6 */
rockchip,camera-hdr-mode = <5>;
port {
sc4238_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
};

44
Documentation/devicetree/bindings/media/i2c/gc4c33.txt Normal file
View File

@@ -0,0 +1,44 @@
* galaxycore,gc4c33 MIPI sensor
Required Properties:
- compatible: should be "galaxycore,gc4c33"
- clocks: reference to the 27M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: High active reset gpio
Attention:
GC4C33 device address 0x29(7bit)
Example:
&i2c1 {
status = "okay";
gc4c33: gc4c33@29 {
compatible = "galaxycore,gc4c33";
reg = <0x29>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "PCORW0009A";
rockchip,camera-module-lens-name = "40IRC-4M";
/* NO_HDR:0 HDR_X2:5 HDR_X3:6 */
rockchip,camera-hdr-mode = <0>;
port {
sc4238_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
};

35
Documentation/devicetree/bindings/media/i2c/imx323.txt Normal file
View File

@@ -0,0 +1,35 @@
* Sony IMX323 DVP sensor
Required Properties:
- compatible: should be "sony,imx323"
- clocks: reference to the 37.125M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
&i2c3: imx323@1a {
compatible = "sony,imx323";
reg = <0x1a>;
clocks = <&cru SCLK_CIF_OUT>;
clock-names = "xvclk";
avdd-supply = <&vcc2v8_dvp>;
dovdd-supply = <&vcc1v8_dvp>;
dvdd-supply = <&vdd1v5_dvp>;
pwdn-gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&dvp_d0d1_m0 &dvp_d2d9_m0
&dvp_d10d11_m0 &cif_clkout_m0>;
port {
imx323_out: endpoint {
remote-endpoint = <&isp0_dvp_in>;
};
};
};

49
Documentation/devicetree/bindings/media/i2c/imx378.txt Normal file
View File

@@ -0,0 +1,49 @@
* Sony IMX378 MIPI sensor
Required Properties:
- compatible: should be "sony,imx378"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: High active reset gpio
Attention:
IMX378 device address 0x1a(7bit);
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
&i2c1 {
status = "okay";
imx378: imx378@1a {
compatible = "sony,imx378";
reg = <0x1a>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "A12N01B";
rockchip,camera-module-lens-name = "48IRC-12M-F18";
/* NO_HDR:0 HDR_X2:5 HDR_X3:6 */
rockchip,camera-hdr-mode = <0>;
port {
sc4238_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2 3 4>;
};
};
};
};

49
Documentation/devicetree/bindings/media/i2c/lt7911d.txt Normal file
View File

@@ -0,0 +1,49 @@
* Lontium lt7911d type-c/DP to MIPI-CSI Bridge
Required Properties:
- compatible: should be "lontium,lt7911d".
- clocks: reference to the 27M xvclk input clock.
- clock-names: should be "xvclk".
- reset-gpios: Low active reset gpio.
- power-gpios: High active power gpio.
- hpd-ctl-gpios: High active hpd control gpio.
If inverted circuit, choose low active.
- plugin-det-gpios: Low active plugin detect gpio.
- interrupts: GPIO connected to the gpio5.
- data-lanes: should be <1 2 3 4> for four-lane operation,
or <1 2> for two-lane operation.
Attention:
LT7911D device address 0x2b(7bit)
Example:
&i2c7 {
status = "okay";
lt7911d: lt7911d@2b {
compatible = "lontium,lt7911d";
status = "okay";
reg = <0x2b>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
clock-names = "xvclk";
interrupt-parent = <&gpio3>;
interrupts = <RK_PD4 IRQ_TYPE_EDGE_RISING>;
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&mipim1_camera1_clk>;
reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
power-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
hpd-ctl-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "LT7911D";
rockchip,camera-module-lens-name = "NC";
port {
lt7911d_out: endpoint {
remote-endpoint = <&hdmi_mipi_in>;
data-lanes = <1 2 3 4>;
};
};
};
};

49
Documentation/devicetree/bindings/media/i2c/lt7911uxc.txt Normal file
View File

@@ -0,0 +1,49 @@
* Lontium lt7911uxc type-c/DP to MIPI-CSI Bridge
Required Properties:
- compatible: should be "lontium,lt7911uxc".
- clocks: reference to the 27M xvclk input clock.
- clock-names: should be "xvclk".
- reset-gpios: Low active reset gpio.
- power-gpios: High active power gpio.
- plugin-det-gpios: Low active plugin detect gpio.
- interrupts: GPIO connected to lt7911uxc gpio0.
- data-lanes: should be <1 2 3 4> for four-lane DPHY,
or <1 2 3> for three-trios CPHY.
Optional Properties:
- bus-type: should be <1> if use CPHY.
should be <4> or default config if use DPHY.
Attention:
LT7911UXC device address 0x43(7bit)
Example:
&i2c5 {
status = "okay";
lt7911uxc: lt7911uxc@43 {
compatible = "lontium,lt7911uxc";
status = "okay";
reg = <0x43>;
clocks = <&ext_cam_clk>;
clock-names = "xvclk";
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_EDGE_RISING>;
power-domains = <&power RK3588_PD_VI>;
reset-gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>;
power-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "LT7911UXC";
rockchip,camera-module-lens-name = "LT7911UXC";
port {
lt7911uxc_out: endpoint {
remote-endpoint = <&dp_mipi_in1>;
bus-type = <1>;
data-lanes = <1 2 3>;
};
};
};
};

48
Documentation/devicetree/bindings/media/i2c/os05a20.txt Normal file
View File

@@ -0,0 +1,48 @@
* Ovti os05a20 MIPI sensor
Required Properties:
- compatible: should be "ovti,os05a20"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
Attention:
os05a20 device address 0x36(7bit) or 0x10(7bit) is decided by SID pin;
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
//rv1126 evb13 board
&i2c1 {
status = "okay";
os05a20: os05a20@36 {
compatible = "ovti,os05a20";
reg = <0x36>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
power-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "JSD3425-C1";
rockchip,camera-module-lens-name = "JSD3425-C1-36IRC-4M-F20";
ir-cut = <&cam_ircut0>;
port {
ucam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
};

44
Documentation/devicetree/bindings/media/i2c/ov12d2q.txt Normal file
View File

@@ -0,0 +1,44 @@
* Omnivision OV12D2Q MIPI CSI-2 sensor
Required Properties:
- compatible: should be "ovti,ov12d2q"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
- pwdn-gpios: High active pwdn gpio
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
i2c0@1c22000 {
ov12d2q: ov12d2q@36 {
compatible = "ovti,ov12d2q";
reg = <0x36>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
ucam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
};

42
Documentation/devicetree/bindings/media/i2c/ov2735.txt Normal file
View File

@@ -0,0 +1,42 @@
* Omnivision OV2735 MIPI CSI-2 sensor
Required Properties:
- compatible: should be "ovti,ov2735"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
i2c0@1c22000 {
...
...
ov2735: ov2735@3c {
compatible = "ovti,ov2735";
reg = <0x3c>;
clocks = <&cru SCLK_CIF_OUT>;
clock-names = "xvclk";
avdd-supply = <&vcc2v8_dvp>;
dovdd-supply = <&vcc1v8_dvp>;
dvdd-supply = <&vcc1v8_dvp>;
pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
port {
ucam_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;
data-lanes = <1 2>;
};
};
};
...
};

44
Documentation/devicetree/bindings/media/i2c/ov2775.txt Normal file
View File

@@ -0,0 +1,44 @@
* Omnivision OV2775 MIPI CSI-2 sensor
Required Properties:
- compatible: should be "ovti,ov2775"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
- pwd-gpios: Low active pwdn gpio
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
i2c0@1c22000 {
ov2775: ov2775@36 {
compatible = "ovti,ov2775";
reg = <0x36>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwd-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
port {
ucam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
};

50
Documentation/devicetree/bindings/media/i2c/ov4688.txt Normal file
View File

@@ -0,0 +1,50 @@
* OmniVision ov4688 MIPI sensor
Required Properties:
- compatible: should be "ovti,ov4688"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
Attention:
SC4238 device address 0x36(7bit);
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
//rv1126 evb13 board
&i2c1 {
status = "okay";
ov4688: ov4688@36 {
compatible = "smartsens,ov4688";
reg = <0x36>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "ODF1981";
rockchip,camera-module-lens-name = "40IRC-4M-F18";
/* NO_HDR:0 HDR_X2:5 HDR_X3:6 */
rockchip,camera-hdr-mode = <0>;
ir-cut = <&cam_ircut0>;
port {
sc4238_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2 3 4>;
};
};
};
};

41
Documentation/devicetree/bindings/media/i2c/ov7725.txt Normal file
View File

@@ -0,0 +1,41 @@
* Omnivision OV7725 MIPI CSI-2 sensor
Required Properties:
- compatible: should be "ovti,ov7725"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
i2c0@1c22000 {
...
...
ov7725: ov7725@21 {
compatible = "ovti,ov7725";
reg = <0x21>;
clocks = <&cru SCLK_CIF_OUT>;
clock-names = "xvclk";
avdd-supply = <&vcc2v8_dvp>;
dovdd-supply = <&vcc1v8_dvp>;
dvdd-supply = <&vcc1v8_dvp>;
pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
port {
ucam_out: endpoint {
remote-endpoint = <&cif_in>;
};
};
};
...
};

42
Documentation/devicetree/bindings/media/i2c/ov7750.txt Normal file
View File

@@ -0,0 +1,42 @@
* Omnivision OV7750 MIPI CSI-2 sensor
Required Properties:
- compatible: should be "ovti,ov7750"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: Low active reset gpio
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
i2c0@1c22000 {
...
...
ov7750: ov7750@60 {
compatible = "ovti,ov7750";
reg = <0x60>;
clocks = <&cru SCLK_CIF_OUT>;
clock-names = "xvclk";
avdd-supply = <&vcc2v8_dvp>;
dovdd-supply = <&vcc1v8_dvp>;
dvdd-supply = <&vcc1v8_dvp>;
pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
port {
ucam_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;
data-lanes = <1>;
};
};
};
...
};

43
Documentation/devicetree/bindings/media/i2c/rk628.txt Normal file
View File

@@ -0,0 +1,43 @@
* RK628 HDMI-RX to MIPI CSI2-TX Bridge
The RK628 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
Required Properties:
- compatible: value should be "rockchip,rk628-csi-v4l2"
- reg: I2C device address
Optional Properties:
- reset-gpios: gpio phandle GPIO connected to the reset pin
- enable-gpios: a GPIO spec for the enable pin
- plugin-det-gpios: HDMI 5V detect pin
- interrupts: GPIO connected to the interrupt pin
- data-lanes: should be <1 2 3 4> for four-lane operation,
or <1 2> for two-lane operation
For further information on the MIPI CSI-2 endpoint node properties, see
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
rk628_csi_v4l2: rk628_csi_v4l2@50 {
reg = <0x50>;
compatible = "rockchip,rk628-csi-v4l2";
interrupt-parent = <&gpio2>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
plugin-det-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "RK628-CSI";
rockchip,camera-module-lens-name = "NC";
port {
hdmiin_out0: endpoint {
remote-endpoint = <&mipi_in>;
data-lanes = <1 2 3 4>;
};
};
};

50
Documentation/devicetree/bindings/media/i2c/sc200ai.txt Normal file
View File

@@ -0,0 +1,50 @@
* smartsens,sc200ai MIPI sensor
Required Properties:
- compatible: should be "smartsens,sc200ai"
- clocks: reference to the 27M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.2 volts
- reset-gpios: High active reset gpio
Attention:
SC4238 device address 0x30(7bit)；
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
&i2c1 {
status = "okay";
sc200ai: sc200ai@30 {
compatible = "smartsens,sc200ai";
reg = <0x30>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "C7234A-400";
rockchip,camera-module-lens-name = "30IRC-2MP-F20";
/* NO_HDR:0 HDR_X2:5 HDR_X3:6 */
rockchip,camera-hdr-mode = <5>;
port {
sc4238_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
};

50
Documentation/devicetree/bindings/media/i2c/sc2239.txt Normal file
View File

@@ -0,0 +1,50 @@
* Smartsens SC2239 MIPI sensor
Required Properties:
- compatible: should be "smartsens,sc2239"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.5 volts
- pwdn-gpios High active reset gpio
- reset-gpios: High active reset gpio
Attention:
SC2239 device address 0x30(7bit) or 0x32(7bit) is decided by SID pin;
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
//rv1126 evb13 board
&i2c1 {
status = "okay";
sc2239: sc2239@30 { // or sc2239: sc2239@32
compatible = "smartsens,sc2239";
reg = <0x30>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "CMK-OT1607-FV1";
rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16";
/* NO_HDR:0 HDR_X2:5 HDR_X3:6 */
rockchip,camera-hdr-mode = <5>;
port {
sc2239_out: endpoint {
remote-endpoint = <&mipi_in_ucam>;
data-lanes = <1>;
};
};
};
};

50
Documentation/devicetree/bindings/media/i2c/sc4238.txt Normal file
View File

@@ -0,0 +1,50 @@
* Smartsens SC4238 MIPI sensor
Required Properties:
- compatible: should be "smartsens,sc4238"
- clocks: reference to the 24M xvclk input clock.
- clock-names: should be "xvclk".
- dovdd-supply: Digital I/O voltage supply, 1.8 volts
- avdd-supply: Analog voltage supply, 2.8 volts
- dvdd-supply: Digital core voltage supply, 1.5 volts
- reset-gpios: Low active reset gpio
Attention:
SC4238 device address 0x30(7bit) or 0x32(7bit) is decided by SID pin;
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
//rv1126 evb13 board
&i2c1 {
status = "okay";
sc4238: sc4238@30 { // or sc4238: sc4238@32
compatible = "smartsens,sc4238";
reg = <0x30>;
clocks = <&cru CLK_MIPICSI_OUT>;
clock-names = "xvclk";
power-domains = <&power RV1126_PD_VI>;
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&mipicsi_clk0>;
avdd-supply = <&vcc_avdd>;
dovdd-supply = <&vcc_dovdd>;
dvdd-supply = <&vcc_dvdd>;
pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "CMK-OT1607-FV1";
rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16";
/* NO_HDR:0 HDR_X2:5 HDR_X3:6 */
rockchip,camera-hdr-mode = <5>;
ir-cut = <&cam_ircut0>;
port {
sc4238_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2 3 4>;
};
};
};
};

59
Documentation/devicetree/bindings/media/i2c/sgm3784.txt Normal file
View File

@@ -0,0 +1,59 @@
* SGM3784 dual flash driver support
Required Properties:
- compatible: Must contain "sgmicro,gsm3784"
- reg: I2C slave address
- enable-gpios: Specifier of the GPIO connected to EN pin
- strobe-gpio: Specifier of the GPIO connected to STROBE pin
- torch-gpio: Specifier of the GPIO connected to GPIO pin,
this pin is for torch mode, if not, will using assist mode.
A discrete LED element connected to the device must be represented by a child
node - see Documentation/devicetree/bindings/leds/common.txt.
Required properties of the LED child node:
- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt
Special properties:
- rockchip,camera-module-index : indicate which camera the flash belongs to.
- rockchip,camera-module-facing : indicate the camera facing.
Example:
&i2c1 {
...
sgm3784: sgm3784@30 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "sgmicro,gsm3784";
reg = <0x30>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
status = "okay";
sgm3784_led0: led@0 {
reg = <0x0>;
led-max-microamp = <299200>;
flash-max-microamp = <1122000>;
flash-max-timeout-us = <1600000>;
};
sgm3784_led1: led@1 {
reg = <0x1>;
led-max-microamp = <299200>;
flash-max-microamp = <1122000>;
flash-max-timeout-us = <1600000>;
};
};
...
ov13850: ov13850@10 {
...
flash-leds = <&sgm3784_led0 &sgm3784_led1>;
...
};
...
}

41
Documentation/devicetree/bindings/media/i2c/virtual-camera.txt Normal file
View File

@@ -0,0 +1,41 @@
* Rockchip Virtual Camera
The virtual sensor supports multiple resolutions output,
such as 1280x720,1920x1080,3840x720,3840x2160,5120x2880.
It also can support RGB24 or raw output formats.
Required Properties:
- compatible: Must be "rockchip,virtual-camera"
- reg: I2C slave address, this value is useless.
- link-frequencies: target mipi clock frequency, half of mipi data rate.
Optional Properties:
- width: output pixel width.
- height: output pixel height.
- bus-format: output bus format, it is a media bus format code.
The device node must contain one 'port' child node for its digital output
video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
&i2c0 {
...
...
vcamera@30 {
compatible = "rockchip,virtual-camera";
reg = <0x30>;
width = <1920>;
height = <1080>;
bus-format = <MEDIA_BUS_FMT_BGGR8_1X8>;
port {
vcamera_out: endpoint {
remote-endpoint = <&dphy_rx_in>;
link-frequencies = /bits/ 64 <500000000>;
};
};
};
...
};

116
Documentation/devicetree/bindings/media/rockchip-cif.txt Normal file
View File

@@ -0,0 +1,116 @@
Rockchip SoC Camera Interface
----------------------------------------------
Rockchip CIF is a camera interface for the Rockchip series of SoCs
like px30, rk3288, rk312x, rk1808, RV1108 to receive frame data from camera or CCIR656 encoder,
and transfer the data into system main memory by AXI bus.
Required properties:
- compatible: value should be one of the following
"rockchip,px30-cif";
"rockchip,rk1808-cif";
"rockchip,rk3128-cif";
"rockchip,rk3288-cif";
- reg : offset and length of the register set for the device.
- interrupts: should contain cif interrupt.
- clocks: phandle to the required clocks.
- clock-names: required clock name.
Optional properties:
- iommus: iommu node attached to cif if exist.
- resets: CRU reset of cif if exist.
port node
-------------------
The device node should contain one 'port' child node with child 'endpoint'
nodes, according to the bindings defined in Documentation/devicetree/bindings/
media/video-interfaces.txt.
- endpoint(parallel):
- remote-endpoint: Connecting to a sensor with a parallel video bus or a mipi csi2 bus.
- parallel_bus properties: Refer to Documentation/devicetree/bindings/
media/video-interfaces.txt.
- mipi csi2 bus properties: Refer to Documentation/devicetree/bindings/
media/video-interfaces.txt.
The port node must contain at least one endpoint.
It could have multiple endpoints, but please note the hardware don't support
two sensors work at a time, they are supposed to work asynchronously.
Device node example
-------------------
cif: cif@ff490000 {
compatible = "rockchip,px30-cif";
reg = <0x0 0xff490000 0x0 0x200>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>;
clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out";
resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>;
reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
power-domains = <&power PX30_PD_VI>;
iommus = <&vip_mmu>;
status = "okay";
port {
cif_in: endpoint {
remote-endpoint = <&gc2155_out>;
vsync-active = <0>;
hsync-active = <1>;
};
};
};
cif: cif@ffae0000 {
compatible = "rockchip,rk1808-cif";
reg = <0x0 0xffae0000 0x0 0x200>, <0x0 0xffb10000 0x0 0x100>;
reg-names = "cif_regs", "csihost_regs";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>,
<&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>,
<&cru PCLK_CSI2HOST>;
clock-names = "aclk_cif", "dclk_cif",
"hclk_cif", "sclk_cif_out",
"pclk_csi2host";
resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
<&cru SRST_CIF_I>, <&cru SRST_CIF_D>,
<&cru SRST_CIF_PCLKIN>;
reset-names = "rst_cif_a", "rst_cif_h",
"rst_cif_i", "rst_cif_d",
"rst_cif_pclkin";
power-domains = <&power RK1808_PD_VIO>;
iommus = <&cif_mmu>;
status = "okay";
port {
cif_in: endpoint@0 {
remote-endpoint = <&dphy_rx_out>;
data-lanes = <1 2 3 4>;
};
};
};
cif: cif@1010a000 {
compatible = "rockchip,rk3128-cif";
reg = <0x1010a000 0x200>;
clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>,
<&cru SCLK_CIF_OUT>;
clock-names = "aclk_cif", "hclk_cif",
"sclk_cif_out";
resets = <&cru SRST_CIF0>;
reset-names = "rst_cif";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* px3se has not iommu attached */
/* iommus = <&cif_mmu>; */
power-domains = <&power RK3128_PD_VIO>;
status = "okay";
port {
cif_in: endpoint {
remote-endpoint = <&adv7181_out>;
vsync-active = <0>;
hsync-active = <1>;
};
};
};

72
Documentation/devicetree/bindings/media/rockchip-isp1.txt Normal file
View File

@@ -0,0 +1,72 @@
Rockchip SoC Image Signal Processing unit v1
----------------------------------------------
Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
which contains image processing, scaling, and compression funcitons.
Required properties:
- compatible: value should be one of the following
"rockchip,rk1808-rkisp1";
"rockchip,rk3288-rkisp1";
"rockchip,rk3326-rkisp1";
"rockchip,rk3368-rkisp1";
"rockchip,rk3399-rkisp1";
- reg : offset and length of the register set for the device.
- interrupts: should contain ISP interrupt.
- clocks: phandle to the required clocks.
- clock-names: required clock name.
- iommus: required a iommu node.
port node
-------------------
The device node should contain one 'port' child node with child 'endpoint'
nodes, according to the bindings defined in Documentation/devicetree/bindings/
media/video-interfaces.txt.
- endpoint(parallel):
- remote-endpoint: Connecting to a sensor with a parallel video bus.
- parallel_bus properties: Refer to Documentation/devicetree/bindings/
media/video-interfaces.txt.
- endpoint(mipi):
- remote-endpoint: Connecting to Rockchip MIPI-DPHY,
which is defined in rockchip-mipi-dphy.txt.
The port node must contain at least one endpoint, either parallel or mipi.
It could have multiple endpoints, but please note the hardware don't support
two sensors work at a time, they are supposed to work asynchronously.
Device node example
-------------------
isp0: isp0@ff910000 {
compatible = "rockchip,rk3399-rkisp1";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP0>,
<&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>,
<&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "clk_isp",
"aclk_isp", "aclk_isp_wrap",
"hclk_isp", "hclk_isp_wrap";
power-domains = <&power RK3399_PD_ISP0>;
iommus = <&isp0_mmu>;
port {
#address-cells = <1>;
#size-cells = <0>;
/* mipi */
isp0_mipi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy_rx0_out>;
};
/* parallel */
isp0_parallel_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov5640_out>;
bus-width = <8>;
};
};
};

136
Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt Normal file
View File

@@ -0,0 +1,136 @@
Rockchip SoC MIPI RX D-PHY
-------------------------------------------------------------
Required properties:
- compatible: value should be one of the following
"rockchip,rk1808-mipi-dphy-rx"
"rockchip,rk3288-mipi-dphy"
"rockchip,rk3326-mipi-dphy"
"rockchip,rk3368-mipi-dphy"
"rockchip,rk3399-mipi-dphy"
"rockchip,rv1126-csi-dphy"
- clocks : list of clock specifiers, corresponding to entries in
clock-names property;
- clock-names: required clock name.
MIPI RX0 D-PHY use registers in "general register files", it
should be a child of the GRF.
MIPI TX1RX1 D-PHY have its own registers, it must have a reg property.
Optional properties:
- reg: offset and length of the register set for the device.
- rockchip,grf: MIPI TX1RX1 D-PHY not only has its own register but also
the GRF, so it is only necessary for MIPI TX1RX1 D-PHY.
port node
-------------------
The device node should contain two 'port' child nodes, according to the bindings
defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
The first port show the sensors connected in this mipi-dphy.
- endpoint:
- remote-endpoint: Linked to a sensor with a MIPI CSI-2 video bus.
- data-lanes : (required) an array specifying active physical MIPI-CSI2
data input lanes and their mapping to logical lanes; the
D-PHY can't reroute lanes, so the array's content should
be consecutive and only its length is meaningful.
For CCP2, v4l2 fwnode endpoint parse this read by u32.
- bus-type: data bus type. Possible values are:
0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656)
1 - MIPI CSI-2 C-PHY, no support
2 - MIPI CSI1, no support
3 - CCP2, using for lvds
The port node must contain at least one endpoint. It could have multiple endpoints
linked to different sensors, but please note that they are not supposed to be
actived at the same time.
The second port should be connected to isp node.
- endpoint:
- remote-endpoint: Linked to Rockchip ISP1, which is defined
in rockchip-isp1.txt.
Device node example
-------------------
grf: syscon@ff770000 {
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
...
mipi_dphy_rx0: mipi-dphy-rx0 {
compatible = "rockchip,rk3399-mipi-dphy";
clocks = <&cru SCLK_MIPIDPHY_REF>,
<&cru SCLK_DPHY_RX0_CFG>,
<&cru PCLK_VIO_GRF>;
clock-names = "dphy-ref", "dphy-cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_wcam: endpoint@0 {
reg = <0>;
remote-endpoint = <&wcam_out>;
data-lanes = <1 2>;
};
mipi_in_ucam: endpoint@1 {
reg = <1>;
remote-endpoint = <&ucam_out>;
data-lanes = <1>;
};
};
port@1 {
reg = <1>;
dphy_rx0_out: endpoint {
remote-endpoint = <&isp0_mipi_in>;
};
};
};
};
};
example for rv1126 node
csi_dphy0 {
compatible = "rockchip,rv1126-csi-dphy";
reg = <0xff4b0000 0x8000>;
clocks = <&cru PCLK_CSIPHY0>;
clock-names = "pclk";
rockchip,grf = <&grf>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&ucam_out0>;
/*data-lanes = <1 2 3 4>; //for mipi*/
data-lanes = <4>; //for lvds, note: this diff to mipi
bus-type = <3>; //for lvds
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp_in>;
};
};
};
};

54
Documentation/devicetree/bindings/media/rockchip-tsp.txt Normal file
View File

@@ -0,0 +1,54 @@
device-tree bindings for rockchip Transport Stream Processing Module (TSP)
TSP is designed for processing Transport Stream Packets,
including receiving TS packets, PID filtering, TS descrambling,
De-multiplexing and TS outputting.Processed data are transferred to
memory buffer which are continued to be processing by software.
Required properties:
- compatible: value should be one of the following
"rockchip,rk312x-tsp";
"rockchip,rk3228-tsp";
"rockchip,rk3288-tsp";
"rockchip,rk3328-tsp";
"rockchip,rk3368-tsp";
- reg : offset and length of the register set for the device.
- interrupts: TSP interrupt specifier.
- interrupts-name: should be "irq_tsp".
- clocks: phandle to TSP sclk/hclk/aclk clocks
- clock-names: should be "clk_tsp", "hclk_tsp" and "aclk_tsp"
- pinctrl-names: use "default"
- pinctrl-0: pin config for iomux
Example:
SoC-specific DT entry:
tsp: tsp@ff050000 {
compatible = "rockchip,rk3328-tsp";
reg = <0x0 0xff050000 0x0 0x10000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_tsp";
clocks = <&cru SCLK_TSP>, <&cru ACLK_TSP>, <&cru HCLK_TSP>;
clock-names = "clk_tsp", "aclk_tsp", "hclk_tsp";
pinctrl-names = "default";
pinctrl-0 = <&tsp_d0
&tsp_d1
&tsp_d2
&tsp_d3
&tsp_d4
&tsp_d5
&tsp_d6
&tsp_d7
&tsp_sync
&tsp_clk
&tsp_fail
&tsp_valid>;
status = "disabled";
};

31
Documentation/devicetree/bindings/mfd/fusb302.txt Normal file
View File

@@ -0,0 +1,31 @@
Fairchild FUSB301 Driver
Required properties:
- compatible: "fairchild,fusb302"
- reg: I2C slave address
- pinctrl-names: Musb be "default"
- pinctrl-0: fusb1_int musb be set to pull up.
- vbus-5v-gpios: enable/disable 5v vbus output
- vbus-other-gpios: enable/disable other high-voltage vbus output
- int-n-gpios: I2C int pin
- fusb302,role: typec port power role
(ROLE_MODE_DRP/ROLE_MODE_DFP/ROLE_MODE_UFP)
- fusb302,try_role: enable try.role function, it would try your wanted
role when detect.
Valid when fusb302,role == ROLE_MODE_DRP.
(ROLE_MODE_DFP/ROLE_MODE_UFP)
example:
fusb1: fusb30x@22 {
compatible = "fairchild,fusb302";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&fusb1_int>;
vbus-5v-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
vbus-other-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
int-n-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
fusb302,role = "ROLE_MODE_DRP";
fusb302,try_role = "ROLE_MODE_DFP";
status = "okay";
};

24
Documentation/devicetree/bindings/mfd/rk1000-core.txt Normal file
View File

@@ -0,0 +1,24 @@
RK1000 Multi-functional device
The RK1000-CORE are RK1000 control register block.
The chip is connected to an i2c bus.
Required properties:
- compatible : "rockchip,rk1000-ctl"
- reg: I2C slave address
- reset-gpios : the reset pin
- clocks : phandle and clock specifier
- clock-names : "mclk"
Example:
rk1000-ctl@40 {
compatible = "rockchip,rk1000-ctl";
reg = <0x40>;
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_bus>;
status = "okay";
};

30
Documentation/devicetree/bindings/mfd/rk618.txt Normal file
View File

@@ -0,0 +1,30 @@
Device-Tree bindings for Rockchip RK618 MFD driver
Required properties:
- compatible: value should be one of the following:
"rockchip,rk618"
- reg: I2C device address.
- clocks: phandle to the clkin clock provider
- clock-names: Must be "clkin"
- reset-gpios: a GPIO spec for the reset pin
Optional properties:
- power-supply: regulator to provide the supply voltage
- enable-gpios: a GPIO spec for the enable pin
Example:
&i2c5 {
status = "okay";
rk618: rk618@50 {
compatible = "rockchip,rk618";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_mclk>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "clkin";
reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
};
};

315
Documentation/devicetree/bindings/mfd/rk809.txt Normal file
View File

@@ -0,0 +1,315 @@
RK809 Power Management Integrated Circuit
Required properties:
- compatible: "rockchip,rk809"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
Optional properties:
- clock-output-names: From common clock binding to override the
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
- vcc3-supply: The input supply for DCDC_REG3
- vcc4-supply: The input supply for DCDC_REG4
- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3
- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6
- vcc7-supply: The input supply for LDO_REG7, LDO_REG8, LDO_REG9
- vcc8-supply: The input supply for SWITCH_REG1
- vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2
Regulators: All the regulators of RK809 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
by a child node of the 'regulators' node.
regulator-name {
/* standard regulator bindings here */
};
Following regulators of the RK809 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK808 datasheet.
- DCDC_REGn
- valid values for n are 1 to 5.
- LDO_REGn
- valid values for n are 1 to 9.
- SWITCH_REGn
- valid values for n are 1 to 2.
The gpio_slp pin is for controlling the pmic states, as below:
reset
power down
sleep
Standard regulator bindings are used inside regulator subnodes. Check
Documentation/devicetree/bindings/regulator/regulator.txt
for more details
Example:
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
pwrkey {
status = "okay";
};
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x1>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc3v3_sys: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc3v3_lcd: SWITCH_REG1 {
regulator-boot-on;
regulator-name = "vcc3v3_lcd";
};
vcc5v0_host: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host";
};
};
rk809_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
}

225
Documentation/devicetree/bindings/mfd/rk816.txt Normal file
View File

@@ -0,0 +1,225 @@
RK816 Power Management Integrated Circuit
Required properties:
- compatible: "rockchip,rk816"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs).
Optional properties:
- clock-output-names: From common clock binding to override the
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- gpio-controller: Specifies that the node is a gpio controller when you attempt to
use the TS pin of RK816 by GPIO general interface.
- #gpio-cells: Should be two. The first cell is the GPIO number and the second cell
is used to specify the GPIO polarity.
- wakeup-source: Flag to indicate this device can wake system (suspend/resume)
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
- vcc3-supply: The input supply for DCDC_REG3
- vcc4-supply: The input supply for DCDC_REG4
- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3
- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6
- regulator-initial-mode: default mode to set on startup
- regulator-initial-mode is set as:
REGULATOR_MODE_FAST 0x1
REGULATOR_MODE_NORMAL 0x2
Regulators: All the regulators of RK816 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
by a child node of the 'regulators' node.
regulator-name {
/* standard regulator bindings here */
};
Following regulators of the RK816 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK816 datasheet.
- DCDC_REGn
- valid values for n are 1 to 4.
- LDO_REGn
- valid values for n are 1 to 6.
Standard regulator bindings are used inside regulator subnodes. Check
Documentation/devicetree/bindings/regulator/regulator.txt
for more details
Gpio, Rtc, Pwrkey: the node are represented like below. When you attempt to enable
the module, setting the "status" to be "okay", otherwise "disabled".
rtc {
status = "okay";
};
pwrkey {
status = "okay";
};
gpio {
status = "okay";
};
Example:
rk816: pmic@1a {
compatible = "rockchip,rk816";
status = "disabled";
reg = <0x1a>;
clock-output-names = "xin32k", "wifibt_32kin";
interrupt-parent = <&gpio0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
gpio-controller;
#gpio-cells = <2>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
rtc {
status = "okay";
};
pwrkey {
status = "okay";
};
gpio {
status = "okay";
};
regulators {
vdd_cpu: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <1>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <1>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-initial-mode = <1>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc33_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_io";
regulator-initial-mode = <1>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_pmu: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_tp: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_tp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc18_lcd: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};

364
Documentation/devicetree/bindings/mfd/rk817.txt Normal file
View File

@@ -0,0 +1,364 @@
RK817 Power Management Integrated Circuit
Required properties:
- compatible: "rockchip,rk817"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
Optional properties:
- clock-output-names: From common clock binding to override the
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
- vcc3-supply: The input supply for DCDC_REG3
- vcc4-supply: The input supply for DCDC_REG4
- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3
- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6
- vcc7-supply: The input supply for LDO_REG7, LDO_REG8, LDO_REG9
- vcc8-supply: The input supply for BOOST
- vcc9-supply: The input supply for OTG_SWITCH
Regulators: All the regulators of RK817 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
by a child node of the 'regulators' node.
regulator-name {
/* standard regulator bindings here */
};
Following regulators of the RK817 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK808 datasheet.
- DCDC_REGn
- valid values for n are 1 to 4.
- LDO_REGn
- valid values for n are 1 to 9.
There are three pins needed config, named "gpio_ts" "gpio_gt" "gpio_slp".
The gpio_gt and gpio_ts pins support the gpio function.
For using a gpio function, dtsi need the following info:
pinctrl-names = "default";
pinctrl-0 = <&rk817_ts_gpio1>, <&rk817_gt_gpio2>;
gpios = <&pinctrl_rk8xx 1 GPIO_ACTIVE_HIGH>,
<&pinctrl_rk8xx 2 GPIO_ACTIVE_HIGH>;
The gpio_slp pin is for controlling the pmic states, as below:
reset
power down
sleep
Standard regulator bindings are used inside regulator subnodes. Check
Documentation/devicetree/bindings/regulator/regulator.txt
for more details
Example:
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc3-supply = <&vccsys>;
vcc4-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vcc_3v0>;
vcc8-supply = <&vccsys>;
vcc9-supply = <&dcdc_boost>;
pwrkey {
status = "okay";
};
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_ts_gpio1: rk817_ts_gpio1 {
pins = "gpio_ts";
function = "pin_fun1";
/* output-low; */
/* input-enable; */
};
rk817_gt_gpio2: rk817_gt_gpio2 {
pins = "gpio_gt";
function = "pin_fun1";
};
rk817_pin_ts: rk817_pin_ts {
pins = "gpio_ts";
function = "pin_fun0";
};
rk817_pin_gt: rk817_pin_gt {
pins = "gpio_gt";
function = "pin_fun0";
};
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x1>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v0: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <0x1>;
regulator-name = "vcc_3v0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc2v5_ddr: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5_ddr";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2500000>;
};
};
vcc1v8_soc: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v0_soc: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vcc1v0_soc";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v0_pmu: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc3v0_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc2v8_dvp: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd1v5_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd1v5_dvp";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
dcdc_boost: BOOST {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <5400000>;
regulator-name = "boost";
};
otg_switch: OTG_SWITCH {
regulator-boot-on;
regulator-name = "otg_switch";
};
};
battery {
compatible = "rk817,battery";
ocv_table = <3500 3625 3685 3697 3718 3735 3748
3760 3774 3788 3802 3816 3834 3853
3877 3908 3946 3975 4018 4071 4106>;
design_capacity = <2500>;
design_qmax = <2750>;
bat_res = <100>;
sleep_enter_current = <300>;
sleep_exit_current = <300>;
sleep_filter_current = <100>;
power_off_thresd = <3500>;
zero_algorithm_vol = <3850>;
max_soc_offset = <60>;
monitor_sec = <5>;
sample_res = <10>;
virtual_power = <1>;
};
charger {
compatible = "rk817,charger";
min_input_voltage = <4500>;
max_input_current = <1500>;
max_chrg_current = <1300>;
max_chrg_voltage = <4200>;
chrg_term_mode = <1>;
chrg_finish_cur = <300>;
virtual_power = <0>;
dc_det_adc = <0>;
extcon = <&u2phy>;
};
rk817_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
}

231
Documentation/devicetree/bindings/mfd/rk818.txt Normal file
View File

@@ -0,0 +1,231 @@
RK818 Power Management Integrated Circuit
Required properties:
- compatible: "rockchip,rk818"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
Optional properties:
- clock-output-names: From common clock binding to override the
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
- vcc3-supply: The input supply for DCDC_REG3
- vcc4-supply: The input supply for DCDC_REG4
- vcc6-supply: The input supply for LDO_REG1, LDO_REG2
- vcc7-supply: The input supply for LDO_REG3, LDO_REG5, LDO_REG7
- vcc8-supply: The input supply for LOD_REG4, LDO_REG6, LDO_REG8
- vcc9-supply: The input supply for LDO_REG9, LDO_REG5, SWITCH_REG
Regulators: All the regulators of RK818 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
by a child node of the 'regulators' node.
regulator-name {
/* standard regulator bindings here */
};
Following regulators of the RK818 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK818 datasheet.
- DCDC_REGn
- valid values for n are 1 to 4.
- LDO_REGn
- valid values for n are 1 to 9.
Standard regulator bindings are used inside regulator subnodes. Check
Documentation/devicetree/bindings/regulator/regulator.txt
for more details
Example:
rk818: pmic@1c {
compatible = "rockchip,rk818";
status = "disabled";
reg = <0x1c>;
clock-output-names = "xin32k", "wifibt_32kin";
interrupt-parent = <&gpio0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&vcc33_io>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc33_io: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33_io";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_pmu: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_tp: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_tp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc18_lcd: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd10_lcd: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_18: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca_codec: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_codec";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_wl: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_wl";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_lcd: SWITCH_REG {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_lcd";
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
};

564
Documentation/devicetree/bindings/mfd/rkx110_x120.yaml Normal file
View File

@@ -0,0 +1,564 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip SerDes MFD driver
description:
Rockchip SerDes MFD driver is a pair chip for long distance transmitting
display image.
maintainers:
- Zhang Yubing <yubing.zhang@rock-chips.com>
properties:
compatible:
enum:
- "rockchip,rkx110", "rockchip,rkx120"
interrupts:
maxItems: 1
description:
The Serdes interrupt is shared by RKX110/RKX120.
clocks:
items:
- description:
clock-names:
items:
- const:
resets:
maxItems: 1
reset-names:
items:
- const:
route:
type: object
description:
A route node descriptor serdes topology
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- route
additionalProperties: false
# example0:
# 1 video source input, 1 channel, 1 lane, 1 remote, 1 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+-------+ +---------+ +---------+ +--------+
| | disp in | | cable0 | | disp out| |
| soc |--------->| RK110 +----------->| RK120 +-------->| screen |
| | | | | | | |
+-------+ +---------+ +---------+ +--------+
examples0:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example1:
# 1 video source input, 2 channel, 1 lane, 1 remote, 1 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+-------+ +---------+ cable0 +---------+ +--------+
| | disp in | +----------->| | disp out| |
| soc |--------->| RK110 | cable1 | RK120 +-------->| screen |
| | | +----------->| | | |
+-------+ +---------+ +---------+ +--------+
examples1:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
num-lanes = <2>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example2:
# 1 video source input, 2 channel, 2 lane, 2 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+---------+ +--------+
cable0 | |disp0 out| |
+------->| RK120 +-------->| screen |
| | | | |
+-------+ +---------+ | +---------+ +--------+
| | disp in | +---+
| soc |--------->| RK110 |
| | | +---+
+-------+ +---------+ | +---------+ +--------+
|cable1 | |disp1 out| |
+------->| RK120 +-------->| screen |
| | | |
+---------+ +--------+
examples2:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
remote1-addr = <0x36>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote1-port0 = <RK_SERDES_LVDS_TX0>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example3:
# 1 video source input, 2 channel, 1 lane, 1 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# lvds0_tx and lvds1_tx
+--------+
lvds0_tx | |
+--->| screen |
+-------+ +---------+ +---------+ | | |
| | disp in | | cable0 | |----+ +--------+
| soc |--------->| RK110 +----------->| RK120 |
| | | | | |----+ +--------+
+-------+ +---------+ +---------+ | | |
+--->| screen |
lvds1_tx | |
+--------+
examples3:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote0-port1 = <RK_SERDES_LVDS_TX1>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example4:
# 2 video source input, 2 channel, 1 lane, 1 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx
# disp out can select follow interface:
# lvds0_tx and lvds1_tx
+--------+
lvds0_tx | |
+--->| screen |
+-------+ disp0_rx +---------+ +---------+ | | |
| |--------->| | cable0 | |----+ +--------+
| soc | disp1_rx | RK110 +----------->| RK120 |
| |--------->| | | |----+ +--------+
+-------+ +---------+ +---------+ | | |
+--->| screen |
lvds1_tx | |
+--------+
examples4:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
local-port1 = <RK_SERDES_LVDS_RX1>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote0-port1 = <RK_SERDES_LVDS_TX1>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example5:
# 2 video source input, 2 channel, 2 lane, 1 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx
# disp out can select follow interface:
# lvds0_tx and lvds1_tx
+--------+
lvds0_tx | |
+--->| screen |
+-------+ disp0_rx +---------+ cable0 +---------+ | | |
| |--------->| +----------->| |----+ +--------+
| soc | disp1_rx | RK110 | cable1 | RK120 |
| |--------->| +----------->| |----+ +--------+
+-------+ +---------+ +---------+ | | |
+--->| screen |
lvds1_tx | |
+--------+
examples5:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
local-port1 = <RK_SERDES_LVDS_RX1>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote0-port1 = <RK_SERDES_LVDS_TX1>;
num-lanes = <2>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example6:
# 2 video source input, 2 channel, 2 lane, 2 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+---------+ +--------+
cable0 | |disp0 out| |
+------->| RK120 +-------->| screen |
| | | | |
+-------+ disp0_rx +---------+ | +---------+ +--------+
| |--------->| +---+
| soc | disp1_rx | RK110 |
| |--------->| +---+
+-------+ +---------+ | +---------+ +--------+
|cable1 | |disp1 out| |
+------->| RK120 +-------->| screen |
| | | |
+---------+ +--------+
examples6:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
remote1-addr = <0x36>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
local-port1 = <RK_SERDES_LVDS_RX1>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote1-port0 = <RK_SERDES_LVDS_TX0>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};

15
Documentation/devicetree/bindings/misc/rockchip-scr.txt Normal file
View File

@@ -0,0 +1,15 @@
* Rockchip Smartcard Reader Controller driver.
Required properties:
- compatible: should be "rockchip-scr"
support smart card reader controller for SoC
such as RK3128, RK322x, RK3288, RK3368, RK3366 and etc.
- reg: Should contain SCR registers location and length
- interrupts: Should contain SCR interrupt
Example:
scr: rkscr@20048000 {
compatible = "rockchip-scr";
reg = <0x20048000 0x4000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};

18
Documentation/devicetree/bindings/net/4g-modem-platdata.txt Normal file
View File

@@ -0,0 +1,18 @@
* Rockchip 4g modem device tree bindings
Required properties:
- compatible : "4g-modem-platdata"
Optional properties:
- 4G,vbat-gpio : 4g modem vbat gpio
- 4G,power-gpio : 4g modem power enable/disable gpio
- 4G,reset-gpio : 4g modem reset gpio
Example:
4G-Modem {
compatible="4g-modem-platdata";
4G,vbat-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
4G,power-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
4G,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
}

33
Documentation/devicetree/bindings/net/can/rk3562_can.txt Normal file
View File

@@ -0,0 +1,33 @@
Rockchip CANFD controller Device Tree Bindings
---------------------------------------------------------
Required properties:
- compatible : Should be:
- "rockchip,rk3562-can" for RK3562 CAN controllers 3.0
- "rockchip,rk3562-canfd" for RK3562 CANFD controllers 3.0
- reg : Physical base address and size of the controller
registers map.
- interrupts : Property with a value describing the interrupt
number.
- clock-names : List of input clock names
- "can_clk", "pclk",
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : List of input reset names
- "can", "can-apb".
Example:
For Dts file:
can0: can0@ff600000 {
compatible = "rockchip,rk3562-can";
reg = <0x0 0xff600000 0x0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
reset-names = "can", "can-apb";
status = "okay";
};

32
Documentation/devicetree/bindings/net/can/rockchip_can.txt Normal file
View File

@@ -0,0 +1,32 @@
Rockchip CAN controller Device Tree Bindings
---------------------------------------------------------
Required properties:
- compatible : Should be:
- "rockchip,can-1.0" for CAN controllers 1.0
- reg : Physical base address and size of the controller
registers map.
- interrupts : Property with a value describing the interrupt
number.
- clock-names : List of input clock names
- "can_clk", "pclk",
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : List of input reset names
- "can", "can-apb".
Example:
For Dts file:
can: can@ff250000 {
compatible = "rockchip,can-1.0";
reg = <0x0 0xff610000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN>, &cru SRST_CAN_P>;
reset-names = "can", "can-apb";
status = "okay";
};

34
Documentation/devicetree/bindings/net/can/rockchip_canfd.txt Normal file
View File

@@ -0,0 +1,34 @@
Rockchip CANFD controller Device Tree Bindings
---------------------------------------------------------
Required properties:
- compatible : Should be:
- "rockchip,canfd-1.0" for CANFD controllers 1.0
- "rockchip,can-2.0" for RK3588 CAN controllers 2.0
- "rockchip,rk3568-can-2.0" for RK3568 CAN controllers 2.0
- reg : Physical base address and size of the controller
registers map.
- interrupts : Property with a value describing the interrupt
number.
- clock-names : List of input clock names
- "can_clk", "pclk",
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : List of input reset names
- "can", "can-apb".
Example:
For Dts file:
can0: can0@fe570000 {
compatible = "rockchip,canfd-1.0";
reg = <0x0 0xfe570000 0x0 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
clock-names = "baudclk", "apb_pclk";
resets = <&cru SRST_CAN0>, &cru SRST_P_CAN0>;
reset-names = "can", "can-apb";
status = "okay";
};

9
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
View File

@@ -24,8 +24,12 @@ select:
- rockchip,rk3366-gmac
- rockchip,rk3368-gmac
- rockchip,rk3399-gmac
- rockchip,rk3528-gmac
- rockchip,rk3562-gmac
- rockchip,rk3568-gmac
- rockchip,rk3576-gmac
- rockchip,rk3588-gmac
- rockchip,rv1106-gmac
- rockchip,rv1108-gmac
- rockchip,rv1126-gmac
required:
@@ -48,11 +52,16 @@ properties:
- rockchip,rk3366-gmac
- rockchip,rk3368-gmac
- rockchip,rk3399-gmac
- rockchip,rk3562-gmac
- rockchip,rv1108-gmac
- items:
- enum:
- rockchip,rk3528-gmac
- rockchip,rk3562-gmac
- rockchip,rk3568-gmac
- rockchip,rk3576-gmac
- rockchip,rk3588-gmac
- rockchip,rv1106-gmac
- rockchip,rv1126-gmac
- const: snps,dwmac-4.20a

5
Documentation/devicetree/bindings/net/snps,dwmac.yaml
View File

@@ -492,6 +492,11 @@ properties:
description:
Frequency division factor for MDC clock.
snps,flow-ctrl:
$ref: /schemas/types.yaml#definitions/uint32
description:
Disable or enable flow control for controller.
mdio:
$ref: mdio.yaml#
unevaluatedProperties: false

3
Documentation/devicetree/bindings/nvmem/rockchip-efuse.yaml
View File

@@ -15,10 +15,13 @@ allOf:
properties:
compatible:
enum:
- rockchip,rk1808-efuse
- rockchip,rk3066a-efuse
- rockchip,rk3128-efuse
- rockchip,rk3188-efuse
- rockchip,rk3228-efuse
- rockchip,rk3288-efuse
- rockchip,rk3288-secure-efuse
- rockchip,rk3328-efuse
- rockchip,rk3368-efuse
- rockchip,rk3399-efuse

Some files were not shown because too many files have changed in this diff Show More