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ARM: dts: rockchip: rk3502: update interrupts for GPIO

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Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I3984166caadad5724eab9580af417f41af3c2ed0
This commit is contained in:
Ye Zhang
2024-12-23 10:32:37 +08:00
committed by Tao Huang
parent 29c2fd4508
commit 8d1876afd2
1 changed files with 21 additions and 5 deletions
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26
arch/arm/boot/dts/rk3502.dtsi
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@@ -1472,7 +1472,10 @@
gpio0: gpio@ff940000 { gpio0: gpio@ff940000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0xff940000 0x200>; reg = <0xff940000 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
gpio-controller; gpio-controller;
@@ -1485,7 +1488,11 @@
gpio1: gpio@ff870000 { gpio1: gpio@ff870000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0xff870000 0x200>; reg = <0xff870000 0x200>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller; gpio-controller;
@@ -1498,7 +1505,10 @@
gpio2: gpio@ff1c0000 { gpio2: gpio@ff1c0000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0xff1c0000 0x200>; reg = <0xff1c0000 0x200>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller; gpio-controller;
@@ -1511,7 +1521,10 @@
gpio3: gpio@ff1d0000 { gpio3: gpio@ff1d0000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0xff1d0000 0x200>; reg = <0xff1d0000 0x200>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller; gpio-controller;
@@ -1524,7 +1537,10 @@
gpio4: gpio@ff1e0000 { gpio4: gpio@ff1e0000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0xff1e0000 0x200>; reg = <0xff1e0000 0x200>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller; gpio-controller;