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arm64: dts: rockchip: rv1126b-pinctrl: Update BT1120/BT656 drive strength

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According to SI test report, BT1120/BT656 drive strength should be
set.

Change-Id: I59aa29fc1c24b0b152fd96a260197fab21790d75
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
This commit is contained in:
Chaoyi Chen
2025-06-20 08:16:19 +00:00
committed by Tao Huang
parent ff5d56d1f3
commit 7d6ab659b7
1 changed files with 35 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
arch/arm64/boot/dts/rockchip/rv1126b-pinctrl.dtsi
View File

@@ -2708,85 +2708,85 @@
bt1120_pins: bt1120-pins {
rockchip,pins =
/* vo_lcdc_clk */
<5 RK_PD3 1 &pcfg_pull_none>,
<5 RK_PD3 1 &pcfg_pull_none_drv_level_4_75>,
/* vo_lcdc_d3 */
<5 RK_PA3 1 &pcfg_pull_none>,
<5 RK_PA3 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d4 */
<5 RK_PA4 1 &pcfg_pull_none>,
<5 RK_PA4 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d5 */
<5 RK_PA5 1 &pcfg_pull_none>,
<5 RK_PA5 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d6 */
<5 RK_PA6 1 &pcfg_pull_none>,
<5 RK_PA6 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d7 */
<5 RK_PA7 1 &pcfg_pull_none>,
<5 RK_PA7 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d10 */
<5 RK_PB2 1 &pcfg_pull_none>,
<5 RK_PB2 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d11 */
<5 RK_PB3 1 &pcfg_pull_none>,
<5 RK_PB3 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d12 */
<5 RK_PB4 1 &pcfg_pull_none>,
<5 RK_PB4 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d13 */
<5 RK_PB5 1 &pcfg_pull_none>,
<5 RK_PB5 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d14 */
<5 RK_PB6 1 &pcfg_pull_none>,
<5 RK_PB6 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d15 */
<5 RK_PB7 1 &pcfg_pull_none>,
<5 RK_PB7 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d19 */
<5 RK_PC3 1 &pcfg_pull_none>,
<5 RK_PC3 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d20 */
<5 RK_PC4 1 &pcfg_pull_none>,
<5 RK_PC4 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d21 */
<5 RK_PC5 1 &pcfg_pull_none>,
<5 RK_PC5 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d22 */
<5 RK_PC6 1 &pcfg_pull_none>,
<5 RK_PC6 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d23 */
<5 RK_PC7 1 &pcfg_pull_none>;
<5 RK_PC7 1 &pcfg_pull_none_drv_level_2_75>;
};
/omit-if-no-ref/
bt656_m0_pins: bt656-m0-pins {
rockchip,pins =
/* vo_lcdc_clk */
<5 RK_PD3 1 &pcfg_pull_none>,
<5 RK_PD3 1 &pcfg_pull_none_drv_level_4_75>,
/* vo_lcdc_d3 */
<5 RK_PA3 1 &pcfg_pull_none>,
<5 RK_PA3 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d4 */
<5 RK_PA4 1 &pcfg_pull_none>,
<5 RK_PA4 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d5 */
<5 RK_PA5 1 &pcfg_pull_none>,
<5 RK_PA5 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d6 */
<5 RK_PA6 1 &pcfg_pull_none>,
<5 RK_PA6 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d7 */
<5 RK_PA7 1 &pcfg_pull_none>,
<5 RK_PA7 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d10 */
<5 RK_PB2 1 &pcfg_pull_none>,
<5 RK_PB2 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d11 */
<5 RK_PB3 1 &pcfg_pull_none>,
<5 RK_PB3 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d12 */
<5 RK_PB4 1 &pcfg_pull_none>;
<5 RK_PB4 1 &pcfg_pull_none_drv_level_2_75>;
};
/omit-if-no-ref/
bt656_m1_pins: bt656-m1-pins {
rockchip,pins =
/* vo_lcdc_clk */
<5 RK_PD3 1 &pcfg_pull_none>,
<5 RK_PD3 1 &pcfg_pull_none_drv_level_4_75>,
/* vo_lcdc_d13 */
<5 RK_PB5 1 &pcfg_pull_none>,
<5 RK_PB5 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d14 */
<5 RK_PB6 1 &pcfg_pull_none>,
<5 RK_PB6 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d15 */
<5 RK_PB7 1 &pcfg_pull_none>,
<5 RK_PB7 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d19 */
<5 RK_PC3 1 &pcfg_pull_none>,
<5 RK_PC3 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d20 */
<5 RK_PC4 1 &pcfg_pull_none>,
<5 RK_PC4 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d21 */
<5 RK_PC5 1 &pcfg_pull_none>,
<5 RK_PC5 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d22 */
<5 RK_PC6 1 &pcfg_pull_none>,
<5 RK_PC6 1 &pcfg_pull_none_drv_level_2_75>,
/* vo_lcdc_d23 */
<5 RK_PC7 1 &pcfg_pull_none>;
<5 RK_PC7 1 &pcfg_pull_none_drv_level_2_75>;
};
/omit-if-no-ref/