mirros/rockchip-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: dts: rockchip: rk3576-cpu-swap: add cache info for A53

Browse Source 
Change-Id: Ib1908adacedb69836159179f8226d6a4e0202550
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2025-05-27 11:44:04 +08:00
committed by Tao Huang
parent 424135148b
commit 72d459a462
1 changed files with 28 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
arch/arm64/boot/dts/rockchip/rk3576-cpu-swap.dtsi
View File

@@ -21,6 +21,13 @@
#cooling-cells = <2>; #cooling-cells = <2>;
dynamic-power-coefficient = <120>; dynamic-power-coefficient = <120>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
}; };
cpu_l1: cpu@001 { cpu_l1: cpu@001 {
@@ -32,6 +39,13 @@
clocks = <&scmi_clk ARMCLK_L>; clocks = <&scmi_clk ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>; operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
}; };
cpu_l2: cpu@002 { cpu_l2: cpu@002 {
@@ -43,6 +57,13 @@
clocks = <&scmi_clk ARMCLK_L>; clocks = <&scmi_clk ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>; operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
}; };
cpu_l3: cpu@003 { cpu_l3: cpu@003 {
@@ -54,6 +75,13 @@
clocks = <&scmi_clk ARMCLK_L>; clocks = <&scmi_clk ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>; operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>; cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
}; };
}; };
}; };