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arm64: dts: qcom: msm8994: Fix CPU6/7 reg values

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[ Upstream commit 47bf59c475 ]

CPU6 and CPU7 were mistakengly pointing to CPU5 reg. Fix it.

Fixes: 02d8091bbc ("arm64: dts: qcom: msm8994: Add a proper CPU map")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220501184016.64138-1-konrad.dybcio@somainline.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Konrad Dybcio
2022-05-01 20:40:16 +02:00
committed by Greg Kroah-Hartman
parent 2c0d10ce00
commit 6bf74a1e74
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/boot/dts/qcom/msm8994.dtsi
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@@ -92,7 +92,7 @@
CPU6: cpu@102 { CPU6: cpu@102 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x0 0x101>; reg = <0x0 0x102>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
}; };
@@ -100,7 +100,7 @@
CPU7: cpu@103 { CPU7: cpu@103 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x0 0x101>; reg = <0x0 0x103>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
}; };