mirros/rockchip-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: dts: rockchip: rk3576: Add trim configure for tsadc

Browse Source 
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I34fbd118ac4b428548f8a5a71c656634a6a703dc
This commit is contained in:
Ye Zhang
2024-07-04 20:58:06 +08:00
parent d8b7089c6a
commit 64422a050b
1 changed files with 75 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

75
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@@ -4407,6 +4407,41 @@
log_leakage: log-leakage@22 {
reg = <0x22 0x1>;
};
bigcore_tsadc_trim_l: bigcore-tsadc-trim-l@24 {
reg = <0x24 0x1>;
};
bigcore_tsadc_trim_h: bigcore-tsadc-trim-h@25 {
reg = <0x25 0x1>;
bits = <0 1>;
};
litcore_tsadc_trim_l: litcore-tsadc-trim-l@26 {
reg = <0x26 0x1>;
};
litcore_tsadc_trim_h: litcore-tsadc-trim-h@27 {
reg = <0x27 0x1>;
bits = <0 1>;
};
ddr_tsadc_trim_l: ddr-tsadc-trim-l@28 {
reg = <0x28 0x1>;
};
ddr_tsadc_trim_h: ddr-tsadc-trim-h@29 {
reg = <0x29 0x1>;
bits = <0 1>;
};
npu_tsadc_trim_l: npu-tsadc-trim-l@2a {
reg = <0x2a 0x1>;
};
npu_tsadc_trim_h: npu-tsadc-trim-h@2b {
reg = <0x2b 0x1>;
bits = <0 1>;
};
gpu_tsadc_trim_l: gpu-tsadc-trim-l@2c {
reg = <0x2c 0x1>;
};
gpu_tsadc_trim_h: gpu-tsadc-trim-h@2d {
reg = <0x2d 0x1>;
bits = <0 1>;
};
cpub_opp_info: cpub-opp-info@30 {
reg = <0x30 0x6>;
};
@@ -4422,6 +4457,13 @@
logic_opp_info: logic-opp-info@4e {
reg = <0x4e 0x6>;
};
soc_tsadc_trim_l: soc-tsadc-trim-l@64 {
reg = <0x64 0x1>;
};
soc_tsadc_trim_h: soc-tsadc-trim-h@65 {
reg = <0x65 0x1>;
bits = <0 1>;
};
};
sai0: sai@2a600000 {
@@ -5515,7 +5557,40 @@
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
tsadc@0 {
reg = <0>;
nvmem-cells = <&soc_tsadc_trim_l>, <&soc_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
tsadc@1 {
reg = <1>;
nvmem-cells = <&bigcore_tsadc_trim_l>, <&bigcore_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
tsadc@2 {
reg = <2>;
nvmem-cells = <&litcore_tsadc_trim_l>, <&litcore_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
tsadc@3 {
reg = <3>;
nvmem-cells = <&ddr_tsadc_trim_l>, <&ddr_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
tsadc@4 {
reg = <4>;
nvmem-cells = <&npu_tsadc_trim_l>, <&npu_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
tsadc@5 {
reg = <5>;
nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
};
};
i2c9: i2c@2ae80000 {