mirros/rockchip-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: dts: rockchip: Add rkisp1 for rk3399

Browse Source 
Change-Id: Ie0eb7088d08f9c0cbd0443b6f9c635ade9b4cc8f
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
This commit is contained in:
Hu Kejun
2018-03-28 19:24:21 +08:00
committed by Tao Huang
parent c05bc80b87
commit 53219cd8f3
2 changed files with 43 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/media/rockchip-isp1.txt
View File

@@ -38,7 +38,7 @@ Device node example
-------------------
isp0: isp0@ff910000 {
compatible = "rockchip,rk3399-cif-isp";
compatible = "rockchip,rk3399-rkisp1";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP0>,

42
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@@ -1558,6 +1558,16 @@
};
};
mipi_dphy_rx0: mipi-dphy-rx0 {
compatible = "rockchip,rk3399-mipi-dphy";
clocks = <&cru SCLK_MIPIDPHY_REF>,
<&cru SCLK_DPHY_RX0_CFG>,
<&cru PCLK_VIO_GRF>;
clock-names = "dphy-ref", "dphy-cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
status = "disabled";
};
pvtm: pvtm {
compatible = "rockchip,rk3399-pvtm";
clocks = <&cru SCLK_PVTM_CORE_L>,
@@ -1879,6 +1889,22 @@
status = "disabled";
};
rkisp1_0: rkisp1@ff910000 {
compatible = "rockchip,rk3399-rkisp1";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP0>,
<&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
<&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "clk_isp",
"aclk_isp", "hclk_isp",
"aclk_isp_wrap", "hclk_isp_wrap";
devfreq = <&dmc>;
power-domains = <&power RK3399_PD_ISP0>;
iommus = <&isp0_mmu>;
status = "disabled";
};
isp0_mmu: iommu@ff914000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
@@ -1892,6 +1918,22 @@
status = "disabled";
};
rkisp1_1: rkisp1@ff920000 {
compatible = "rockchip,rk3399-rkisp1";
reg = <0x0 0xff920000 0x0 0x4000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_ISP1>,
<&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
<&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
clock-names = "clk_isp",
"aclk_isp", "hclk_isp",
"aclk_isp_wrap", "hclk_isp_wrap";
devfreq = <&dmc>;
power-domains = <&power RK3399_PD_ISP1>;
iommus = <&isp1_mmu>;
status = "disabled";
};
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;