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Merge remote-tracking branches 'asoc/topic/cs53l30', 'asoc/topic/cygnus', 'asoc/topic/da7219' and 'asoc/topic/davinci' into asoc-next

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This commit is contained in:
Mark Brown
2016-07-24 22:07:31 +01:00
parent 5600eab2df 1708796fc1 1200a7d9b2 a01b89336f 272ee030eb
commit 3ceeda1cbe
19 changed files with 4391 additions and 77 deletions
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67
Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt Normal file
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@@ -0,0 +1,67 @@
BROADCOM Cygnus Audio I2S/TDM/SPDIF controller
Required properties:
- compatible : "brcm,cygnus-audio"
- #address-cells: 32bit valued, 1 cell.
- #size-cells: 32bit valued, 0 cell.
- reg : Should contain audio registers location and length
- reg-names: names of the registers listed in "reg" property
Valid names are "aud" and "i2s_in". "aud" contains a
set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains
a set of I2S_IN registers.
- clocks: PLL and leaf clocks used by audio ports
- assigned-clocks: PLL and leaf clocks
- assigned-clock-parents: parent clocks of the assigned clocks
(usually the PLL)
- assigned-clock-rates: List of clock frequencies of the
assigned clocks
- clock-names: names of 3 leaf clocks used by audio ports
Valid names are "ch0_audio", "ch1_audio", "ch2_audio"
- interrupts: audio DMA interrupt number
SSP Subnode properties:
- reg: The index of ssp port interface to use
Valid value are 0, 1, 2, or 3 (for spdif)
Example:
cygnus_audio: audio@180ae000 {
compatible = "brcm,cygnus-audio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;
reg-names = "aud", "i2s_in";
clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
<&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
<&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
<&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
<&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
<&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
assigned-clock-rates = <1769470191>,
<0>,
<0>,
<0>;
clock-names = "ch0_audio", "ch1_audio", "ch2_audio";
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
ssp0: ssp_port@0 {
reg = <0>;
status = "okay";
};
ssp1: ssp_port@1 {
reg = <1>;
status = "disabled";
};
ssp2: ssp_port@2 {
reg = <2>;
status = "disabled";
};
spdif: spdif_port@3 {
reg = <3>;
status = "disabled";
};
};

44
Documentation/devicetree/bindings/sound/cs53l30.txt Normal file
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@@ -0,0 +1,44 @@
CS53L30 audio CODEC
Required properties:
- compatible : "cirrus,cs53l30"
- reg : the I2C address of the device
- VA-supply, VP-supply : power supplies for the device,
as covered in Documentation/devicetree/bindings/regulator/regulator.txt.
Optional properties:
- reset-gpios : a GPIO spec for the reset pin.
- mute-gpios : a GPIO spec for the MUTE pin. The active state can be either
GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW, which would be handled
by the driver automatically.
- cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin.
0 = Hi-Z
1 = 1.80 V
2 = 2.75 V
- cirrus,use-sdout2 : This is a boolean property. If present, it indicates
the hardware design connects both SDOUT1 and SDOUT2
pins to output data. Otherwise, it indicates that
only SDOUT1 is connected for data output.
* CS53l30 supports 4-channel data output in the same
* frame using two different ways:
* 1) Normal I2S mode on two data pins -- each SDOUT
* carries 2-channel data in the same time.
* 2) TDM mode on one signle data pin -- SDOUT1 carries
* 4-channel data per frame.
Example:
codec: cs53l30@48 {
compatible = "cirrus,cs53l30";
reg = <0x48>;
reset-gpios = <&gpio 54 0>;
VA-supply = <&cs53l30_va>;
VP-supply = <&cs53l30_vp>;
};

28
drivers/base/property.c
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@@ -887,6 +887,34 @@ struct fwnode_handle *device_get_next_child_node(struct device *dev,
} }
EXPORT_SYMBOL_GPL(device_get_next_child_node); EXPORT_SYMBOL_GPL(device_get_next_child_node);
/**
* device_get_named_child_node - Return first matching named child node handle
* @dev: Device to find the named child node for.
* @childname: String to match child node name against.
*/
struct fwnode_handle *device_get_named_child_node(struct device *dev,
const char *childname)
{
struct fwnode_handle *child;
/*
* Find first matching named child node of this device.
* For ACPI this will be a data only sub-node.
*/
device_for_each_child_node(dev, child) {
if (is_of_node(child)) {
if (!of_node_cmp(to_of_node(child)->name, childname))
return child;
} else if (is_acpi_data_node(child)) {
if (acpi_data_node_match(child, childname))
return child;
}
}
return NULL;
}
EXPORT_SYMBOL_GPL(device_get_named_child_node);
/** /**
* fwnode_handle_put - Drop reference to a device node * fwnode_handle_put - Drop reference to a device node
* @fwnode: Pointer to the device node to drop the reference to. * @fwnode: Pointer to the device node to drop the reference to.

7
include/acpi/acpi_bus.h
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@@ -420,6 +420,13 @@ static inline struct acpi_data_node *to_acpi_data_node(struct fwnode_handle *fwn
container_of(fwnode, struct acpi_data_node, fwnode) : NULL; container_of(fwnode, struct acpi_data_node, fwnode) : NULL;
} }
static inline bool acpi_data_node_match(struct fwnode_handle *fwnode,
const char *name)
{
return is_acpi_data_node(fwnode) ?
(!strcmp(to_acpi_data_node(fwnode)->name, name)) : false;
}
static inline struct fwnode_handle *acpi_fwnode_handle(struct acpi_device *adev) static inline struct fwnode_handle *acpi_fwnode_handle(struct acpi_device *adev)
{ {
return &adev->fwnode; return &adev->fwnode;

6
include/linux/acpi.h
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@@ -568,6 +568,12 @@ static inline struct acpi_data_node *to_acpi_data_node(struct fwnode_handle *fwn
return NULL; return NULL;
} }
static inline bool acpi_data_node_match(struct fwnode_handle *fwnode,
const char *name)
{
return false;
}
static inline struct fwnode_handle *acpi_fwnode_handle(struct acpi_device *adev) static inline struct fwnode_handle *acpi_fwnode_handle(struct acpi_device *adev)
{ {
return NULL; return NULL;

14
include/linux/of.h
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@@ -238,13 +238,6 @@ static inline unsigned long of_read_ulong(const __be32 *cell, int size)
#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1 #define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
#endif #endif
/* Default string compare functions, Allow arch asm/prom.h to override */
#if !defined(of_compat_cmp)
#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2))
#define of_prop_cmp(s1, s2) strcmp((s1), (s2))
#define of_node_cmp(s1, s2) strcasecmp((s1), (s2))
#endif
#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags) #define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags) #define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
@@ -726,6 +719,13 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag
#define of_match_node(_matches, _node) NULL #define of_match_node(_matches, _node) NULL
#endif /* CONFIG_OF */ #endif /* CONFIG_OF */
/* Default string compare functions, Allow arch asm/prom.h to override */
#if !defined(of_compat_cmp)
#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2))
#define of_prop_cmp(s1, s2) strcmp((s1), (s2))
#define of_node_cmp(s1, s2) strcasecmp((s1), (s2))
#endif
#if defined(CONFIG_OF) && defined(CONFIG_NUMA) #if defined(CONFIG_OF) && defined(CONFIG_NUMA)
extern int of_node_to_nid(struct device_node *np); extern int of_node_to_nid(struct device_node *np);
#else #else

3
include/linux/property.h
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@@ -77,6 +77,9 @@ struct fwnode_handle *device_get_next_child_node(struct device *dev,
for (child = device_get_next_child_node(dev, NULL); child; \ for (child = device_get_next_child_node(dev, NULL); child; \
child = device_get_next_child_node(dev, child)) child = device_get_next_child_node(dev, child))
struct fwnode_handle *device_get_named_child_node(struct device *dev,
const char *childname);
void fwnode_handle_put(struct fwnode_handle *fwnode); void fwnode_handle_put(struct fwnode_handle *fwnode);
unsigned int device_get_child_node_count(struct device *dev); unsigned int device_get_child_node_count(struct device *dev);

9
sound/soc/bcm/Kconfig
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@@ -7,3 +7,12 @@ config SND_BCM2835_SOC_I2S
Say Y or M if you want to add support for codecs attached to Say Y or M if you want to add support for codecs attached to
the BCM2835 I2S interface. You will also need the BCM2835 I2S interface. You will also need
to select the audio interfaces to support below. to select the audio interfaces to support below.
config SND_SOC_CYGNUS
tristate "SoC platform audio for Broadcom Cygnus chips"
depends on ARCH_BCM_CYGNUS || COMPILE_TEST
help
Say Y if you want to add support for ASoC audio on Broadcom
Cygnus chips (bcm958300, bcm958305, bcm911360)
If you don't know what to do here, say N.

5
sound/soc/bcm/Makefile
View File

@@ -3,3 +3,8 @@ snd-soc-bcm2835-i2s-objs := bcm2835-i2s.o
obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o
# CYGNUS Platform Support
snd-soc-cygnus-objs := cygnus-pcm.o cygnus-ssp.o
obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-cygnus.o

861
sound/soc/bcm/cygnus-pcm.c Normal file
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@@ -0,0 +1,861 @@
/*
* Copyright (C) 2014-2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/debugfs.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "cygnus-ssp.h"
/* Register offset needed for ASoC PCM module */
#define INTH_R5F_STATUS_OFFSET 0x040
#define INTH_R5F_CLEAR_OFFSET 0x048
#define INTH_R5F_MASK_SET_OFFSET 0x050
#define INTH_R5F_MASK_CLEAR_OFFSET 0x054
#define BF_REARM_FREE_MARK_OFFSET 0x344
#define BF_REARM_FULL_MARK_OFFSET 0x348
/* Ring Buffer Ctrl Regs --- Start */
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_RDADDR_REG_BASE */
#define SRC_RBUF_0_RDADDR_OFFSET 0x500
#define SRC_RBUF_1_RDADDR_OFFSET 0x518
#define SRC_RBUF_2_RDADDR_OFFSET 0x530
#define SRC_RBUF_3_RDADDR_OFFSET 0x548
#define SRC_RBUF_4_RDADDR_OFFSET 0x560
#define SRC_RBUF_5_RDADDR_OFFSET 0x578
#define SRC_RBUF_6_RDADDR_OFFSET 0x590
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_WRADDR_REG_BASE */
#define SRC_RBUF_0_WRADDR_OFFSET 0x504
#define SRC_RBUF_1_WRADDR_OFFSET 0x51c
#define SRC_RBUF_2_WRADDR_OFFSET 0x534
#define SRC_RBUF_3_WRADDR_OFFSET 0x54c
#define SRC_RBUF_4_WRADDR_OFFSET 0x564
#define SRC_RBUF_5_WRADDR_OFFSET 0x57c
#define SRC_RBUF_6_WRADDR_OFFSET 0x594
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_BASEADDR_REG_BASE */
#define SRC_RBUF_0_BASEADDR_OFFSET 0x508
#define SRC_RBUF_1_BASEADDR_OFFSET 0x520
#define SRC_RBUF_2_BASEADDR_OFFSET 0x538
#define SRC_RBUF_3_BASEADDR_OFFSET 0x550
#define SRC_RBUF_4_BASEADDR_OFFSET 0x568
#define SRC_RBUF_5_BASEADDR_OFFSET 0x580
#define SRC_RBUF_6_BASEADDR_OFFSET 0x598
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_ENDADDR_REG_BASE */
#define SRC_RBUF_0_ENDADDR_OFFSET 0x50c
#define SRC_RBUF_1_ENDADDR_OFFSET 0x524
#define SRC_RBUF_2_ENDADDR_OFFSET 0x53c
#define SRC_RBUF_3_ENDADDR_OFFSET 0x554
#define SRC_RBUF_4_ENDADDR_OFFSET 0x56c
#define SRC_RBUF_5_ENDADDR_OFFSET 0x584
#define SRC_RBUF_6_ENDADDR_OFFSET 0x59c
/* AUD_FMM_BF_CTRL_SOURCECH_RINGBUF_X_FREE_MARK_REG_BASE */
#define SRC_RBUF_0_FREE_MARK_OFFSET 0x510
#define SRC_RBUF_1_FREE_MARK_OFFSET 0x528
#define SRC_RBUF_2_FREE_MARK_OFFSET 0x540
#define SRC_RBUF_3_FREE_MARK_OFFSET 0x558
#define SRC_RBUF_4_FREE_MARK_OFFSET 0x570
#define SRC_RBUF_5_FREE_MARK_OFFSET 0x588
#define SRC_RBUF_6_FREE_MARK_OFFSET 0x5a0
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_RDADDR_REG_BASE */
#define DST_RBUF_0_RDADDR_OFFSET 0x5c0
#define DST_RBUF_1_RDADDR_OFFSET 0x5d8
#define DST_RBUF_2_RDADDR_OFFSET 0x5f0
#define DST_RBUF_3_RDADDR_OFFSET 0x608
#define DST_RBUF_4_RDADDR_OFFSET 0x620
#define DST_RBUF_5_RDADDR_OFFSET 0x638
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_WRADDR_REG_BASE */
#define DST_RBUF_0_WRADDR_OFFSET 0x5c4
#define DST_RBUF_1_WRADDR_OFFSET 0x5dc
#define DST_RBUF_2_WRADDR_OFFSET 0x5f4
#define DST_RBUF_3_WRADDR_OFFSET 0x60c
#define DST_RBUF_4_WRADDR_OFFSET 0x624
#define DST_RBUF_5_WRADDR_OFFSET 0x63c
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_BASEADDR_REG_BASE */
#define DST_RBUF_0_BASEADDR_OFFSET 0x5c8
#define DST_RBUF_1_BASEADDR_OFFSET 0x5e0
#define DST_RBUF_2_BASEADDR_OFFSET 0x5f8
#define DST_RBUF_3_BASEADDR_OFFSET 0x610
#define DST_RBUF_4_BASEADDR_OFFSET 0x628
#define DST_RBUF_5_BASEADDR_OFFSET 0x640
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_ENDADDR_REG_BASE */
#define DST_RBUF_0_ENDADDR_OFFSET 0x5cc
#define DST_RBUF_1_ENDADDR_OFFSET 0x5e4
#define DST_RBUF_2_ENDADDR_OFFSET 0x5fc
#define DST_RBUF_3_ENDADDR_OFFSET 0x614
#define DST_RBUF_4_ENDADDR_OFFSET 0x62c
#define DST_RBUF_5_ENDADDR_OFFSET 0x644
/* AUD_FMM_BF_CTRL_DESTCH_RINGBUF_X_FULL_MARK_REG_BASE */
#define DST_RBUF_0_FULL_MARK_OFFSET 0x5d0
#define DST_RBUF_1_FULL_MARK_OFFSET 0x5e8
#define DST_RBUF_2_FULL_MARK_OFFSET 0x600
#define DST_RBUF_3_FULL_MARK_OFFSET 0x618
#define DST_RBUF_4_FULL_MARK_OFFSET 0x630
#define DST_RBUF_5_FULL_MARK_OFFSET 0x648
/* Ring Buffer Ctrl Regs --- End */
/* Error Status Regs --- Start */
/* AUD_FMM_BF_ESR_ESRX_STATUS_REG_BASE */
#define ESR0_STATUS_OFFSET 0x900
#define ESR1_STATUS_OFFSET 0x918
#define ESR2_STATUS_OFFSET 0x930
#define ESR3_STATUS_OFFSET 0x948
#define ESR4_STATUS_OFFSET 0x960
/* AUD_FMM_BF_ESR_ESRX_STATUS_CLEAR_REG_BASE */
#define ESR0_STATUS_CLR_OFFSET 0x908
#define ESR1_STATUS_CLR_OFFSET 0x920
#define ESR2_STATUS_CLR_OFFSET 0x938
#define ESR3_STATUS_CLR_OFFSET 0x950
#define ESR4_STATUS_CLR_OFFSET 0x968
/* AUD_FMM_BF_ESR_ESRX_MASK_REG_BASE */
#define ESR0_MASK_STATUS_OFFSET 0x90c
#define ESR1_MASK_STATUS_OFFSET 0x924
#define ESR2_MASK_STATUS_OFFSET 0x93c
#define ESR3_MASK_STATUS_OFFSET 0x954
#define ESR4_MASK_STATUS_OFFSET 0x96c
/* AUD_FMM_BF_ESR_ESRX_MASK_SET_REG_BASE */
#define ESR0_MASK_SET_OFFSET 0x910
#define ESR1_MASK_SET_OFFSET 0x928
#define ESR2_MASK_SET_OFFSET 0x940
#define ESR3_MASK_SET_OFFSET 0x958
#define ESR4_MASK_SET_OFFSET 0x970
/* AUD_FMM_BF_ESR_ESRX_MASK_CLEAR_REG_BASE */
#define ESR0_MASK_CLR_OFFSET 0x914
#define ESR1_MASK_CLR_OFFSET 0x92c
#define ESR2_MASK_CLR_OFFSET 0x944
#define ESR3_MASK_CLR_OFFSET 0x95c
#define ESR4_MASK_CLR_OFFSET 0x974
/* Error Status Regs --- End */
#define R5F_ESR0_SHIFT 0 /* esr0 = fifo underflow */
#define R5F_ESR1_SHIFT 1 /* esr1 = ringbuf underflow */
#define R5F_ESR2_SHIFT 2 /* esr2 = ringbuf overflow */
#define R5F_ESR3_SHIFT 3 /* esr3 = freemark */
#define R5F_ESR4_SHIFT 4 /* esr4 = fullmark */
/* Mask for R5F register. Set all relevant interrupt for playback handler */
#define ANY_PLAYBACK_IRQ (BIT(R5F_ESR0_SHIFT) | \
BIT(R5F_ESR1_SHIFT) | \
BIT(R5F_ESR3_SHIFT))
/* Mask for R5F register. Set all relevant interrupt for capture handler */
#define ANY_CAPTURE_IRQ (BIT(R5F_ESR2_SHIFT) | BIT(R5F_ESR4_SHIFT))
/*
* PERIOD_BYTES_MIN is the number of bytes to at which the interrupt will tick.
* This number should be a multiple of 256. Minimum value is 256
*/
#define PERIOD_BYTES_MIN 0x100
static const struct snd_pcm_hardware cygnus_pcm_hw = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
/* A period is basically an interrupt */
.period_bytes_min = PERIOD_BYTES_MIN,
.period_bytes_max = 0x10000,
/* period_min/max gives range of approx interrupts per buffer */
.periods_min = 2,
.periods_max = 8,
/*
* maximum buffer size in bytes = period_bytes_max * periods_max
* We allocate this amount of data for each enabled channel
*/
.buffer_bytes_max = 4 * 0x8000,
};
static u64 cygnus_dma_dmamask = DMA_BIT_MASK(32);
static struct cygnus_aio_port *cygnus_dai_get_dma_data(
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
return snd_soc_dai_get_dma_data(soc_runtime->cpu_dai, substream);
}
static void ringbuf_set_initial(void __iomem *audio_io,
struct ringbuf_regs *p_rbuf,
bool is_playback,
u32 start,
u32 periodsize,
u32 bufsize)
{
u32 initial_rd;
u32 initial_wr;
u32 end;
u32 fmark_val; /* free or full mark */
p_rbuf->period_bytes = periodsize;
p_rbuf->buf_size = bufsize;
if (is_playback) {
/* Set the pointers to indicate full (flip uppermost bit) */
initial_rd = start;
initial_wr = initial_rd ^ BIT(31);
} else {
/* Set the pointers to indicate empty */
initial_wr = start;
initial_rd = initial_wr;
}
end = start + bufsize - 1;
/*
* The interrupt will fire when free/full mark is *exceeded*
* The fmark value must be multiple of PERIOD_BYTES_MIN so set fmark
* to be PERIOD_BYTES_MIN less than the period size.
*/
fmark_val = periodsize - PERIOD_BYTES_MIN;
writel(start, audio_io + p_rbuf->baseaddr);
writel(end, audio_io + p_rbuf->endaddr);
writel(fmark_val, audio_io + p_rbuf->fmark);
writel(initial_rd, audio_io + p_rbuf->rdaddr);
writel(initial_wr, audio_io + p_rbuf->wraddr);
}
static int configure_ringbuf_regs(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
struct ringbuf_regs *p_rbuf;
int status = 0;
aio = cygnus_dai_get_dma_data(substream);
/* Map the ssp portnum to a set of ring buffers. */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
p_rbuf = &aio->play_rb_regs;
switch (aio->portnum) {
case 0:
*p_rbuf = RINGBUF_REG_PLAYBACK(0);
break;
case 1:
*p_rbuf = RINGBUF_REG_PLAYBACK(2);
break;
case 2:
*p_rbuf = RINGBUF_REG_PLAYBACK(4);
break;
case 3: /* SPDIF */
*p_rbuf = RINGBUF_REG_PLAYBACK(6);
break;
default:
status = -EINVAL;
}
} else {
p_rbuf = &aio->capture_rb_regs;
switch (aio->portnum) {
case 0:
*p_rbuf = RINGBUF_REG_CAPTURE(0);
break;
case 1:
*p_rbuf = RINGBUF_REG_CAPTURE(2);
break;
case 2:
*p_rbuf = RINGBUF_REG_CAPTURE(4);
break;
default:
status = -EINVAL;
}
}
return status;
}
static struct ringbuf_regs *get_ringbuf(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
struct ringbuf_regs *p_rbuf = NULL;
aio = cygnus_dai_get_dma_data(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
p_rbuf = &aio->play_rb_regs;
else
p_rbuf = &aio->capture_rb_regs;
return p_rbuf;
}
static void enable_intr(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
u32 clear_mask;
aio = cygnus_dai_get_dma_data(substream);
/* The port number maps to the bit position to be cleared */
clear_mask = BIT(aio->portnum);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Clear interrupt status before enabling them */
writel(clear_mask, aio->cygaud->audio + ESR0_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR1_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR3_STATUS_CLR_OFFSET);
/* Unmask the interrupts of the given port*/
writel(clear_mask, aio->cygaud->audio + ESR0_MASK_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR1_MASK_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR3_MASK_CLR_OFFSET);
writel(ANY_PLAYBACK_IRQ,
aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
} else {
writel(clear_mask, aio->cygaud->audio + ESR2_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR4_STATUS_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR2_MASK_CLR_OFFSET);
writel(clear_mask, aio->cygaud->audio + ESR4_MASK_CLR_OFFSET);
writel(ANY_CAPTURE_IRQ,
aio->cygaud->audio + INTH_R5F_MASK_CLEAR_OFFSET);
}
}
static void disable_intr(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct cygnus_aio_port *aio;
u32 set_mask;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(rtd->cpu_dai->dev, "%s on port %d\n", __func__, aio->portnum);
/* The port number maps to the bit position to be set */
set_mask = BIT(aio->portnum);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Mask the interrupts of the given port*/
writel(set_mask, aio->cygaud->audio + ESR0_MASK_SET_OFFSET);
writel(set_mask, aio->cygaud->audio + ESR1_MASK_SET_OFFSET);
writel(set_mask, aio->cygaud->audio + ESR3_MASK_SET_OFFSET);
} else {
writel(set_mask, aio->cygaud->audio + ESR2_MASK_SET_OFFSET);
writel(set_mask, aio->cygaud->audio + ESR4_MASK_SET_OFFSET);
}
}
static int cygnus_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
enable_intr(substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
disable_intr(substream);
break;
default:
ret = -EINVAL;
}
return ret;
}
static void cygnus_pcm_period_elapsed(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
struct ringbuf_regs *p_rbuf = NULL;
u32 regval;
aio = cygnus_dai_get_dma_data(substream);
p_rbuf = get_ringbuf(substream);
/*
* If free/full mark interrupt occurs, provide timestamp
* to ALSA and update appropriate idx by period_bytes
*/
snd_pcm_period_elapsed(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Set the ring buffer to full */
regval = readl(aio->cygaud->audio + p_rbuf->rdaddr);
regval = regval ^ BIT(31);
writel(regval, aio->cygaud->audio + p_rbuf->wraddr);
} else {
/* Set the ring buffer to empty */
regval = readl(aio->cygaud->audio + p_rbuf->wraddr);
writel(regval, aio->cygaud->audio + p_rbuf->rdaddr);
}
}
/*
* ESR0/1/3 status Description
* 0x1 I2S0_out port caused interrupt
* 0x2 I2S1_out port caused interrupt
* 0x4 I2S2_out port caused interrupt
* 0x8 SPDIF_out port caused interrupt
*/
static void handle_playback_irq(struct cygnus_audio *cygaud)
{
void __iomem *audio_io;
u32 port;
u32 esr_status0, esr_status1, esr_status3;
audio_io = cygaud->audio;
/*
* ESR status gets updates with/without interrupts enabled.
* So, check the ESR mask, which provides interrupt enable/
* disable status and use it to determine which ESR status
* should be serviced.
*/
esr_status0 = readl(audio_io + ESR0_STATUS_OFFSET);
esr_status0 &= ~readl(audio_io + ESR0_MASK_STATUS_OFFSET);
esr_status1 = readl(audio_io + ESR1_STATUS_OFFSET);
esr_status1 &= ~readl(audio_io + ESR1_MASK_STATUS_OFFSET);
esr_status3 = readl(audio_io + ESR3_STATUS_OFFSET);
esr_status3 &= ~readl(audio_io + ESR3_MASK_STATUS_OFFSET);
for (port = 0; port < CYGNUS_MAX_PLAYBACK_PORTS; port++) {
u32 esrmask = BIT(port);
/*
* Ringbuffer or FIFO underflow
* If we get this interrupt then, it is also true that we have
* not yet responded to the freemark interrupt.
* Log a debug message. The freemark handler below will
* handle getting everything going again.
*/
if ((esrmask & esr_status1) || (esrmask & esr_status0)) {
dev_dbg(cygaud->dev,
"Underrun: esr0=0x%x, esr1=0x%x esr3=0x%x\n",
esr_status0, esr_status1, esr_status3);
}
/*
* Freemark is hit. This is the normal interrupt.
* In typical operation the read and write regs will be equal
*/
if (esrmask & esr_status3) {
struct snd_pcm_substream *playstr;
playstr = cygaud->portinfo[port].play_stream;
cygnus_pcm_period_elapsed(playstr);
}
}
/* Clear ESR interrupt */
writel(esr_status0, audio_io + ESR0_STATUS_CLR_OFFSET);
writel(esr_status1, audio_io + ESR1_STATUS_CLR_OFFSET);
writel(esr_status3, audio_io + ESR3_STATUS_CLR_OFFSET);
/* Rearm freemark logic by writing 1 to the correct bit */
writel(esr_status3, audio_io + BF_REARM_FREE_MARK_OFFSET);
}
/*
* ESR2/4 status Description
* 0x1 I2S0_in port caused interrupt
* 0x2 I2S1_in port caused interrupt
* 0x4 I2S2_in port caused interrupt
*/
static void handle_capture_irq(struct cygnus_audio *cygaud)
{
void __iomem *audio_io;
u32 port;
u32 esr_status2, esr_status4;
audio_io = cygaud->audio;
/*
* ESR status gets updates with/without interrupts enabled.
* So, check the ESR mask, which provides interrupt enable/
* disable status and use it to determine which ESR status
* should be serviced.
*/
esr_status2 = readl(audio_io + ESR2_STATUS_OFFSET);
esr_status2 &= ~readl(audio_io + ESR2_MASK_STATUS_OFFSET);
esr_status4 = readl(audio_io + ESR4_STATUS_OFFSET);
esr_status4 &= ~readl(audio_io + ESR4_MASK_STATUS_OFFSET);
for (port = 0; port < CYGNUS_MAX_CAPTURE_PORTS; port++) {
u32 esrmask = BIT(port);
/*
* Ringbuffer or FIFO overflow
* If we get this interrupt then, it is also true that we have
* not yet responded to the fullmark interrupt.
* Log a debug message. The fullmark handler below will
* handle getting everything going again.
*/
if (esrmask & esr_status2)
dev_dbg(cygaud->dev,
"Overflow: esr2=0x%x\n", esr_status2);
if (esrmask & esr_status4) {
struct snd_pcm_substream *capstr;
capstr = cygaud->portinfo[port].capture_stream;
cygnus_pcm_period_elapsed(capstr);
}
}
writel(esr_status2, audio_io + ESR2_STATUS_CLR_OFFSET);
writel(esr_status4, audio_io + ESR4_STATUS_CLR_OFFSET);
/* Rearm fullmark logic by writing 1 to the correct bit */
writel(esr_status4, audio_io + BF_REARM_FULL_MARK_OFFSET);
}
static irqreturn_t cygnus_dma_irq(int irq, void *data)
{
u32 r5_status;
struct cygnus_audio *cygaud = data;
/*
* R5 status bits Description
* 0 ESR0 (playback FIFO interrupt)
* 1 ESR1 (playback rbuf interrupt)
* 2 ESR2 (capture rbuf interrupt)
* 3 ESR3 (Freemark play. interrupt)
* 4 ESR4 (Fullmark capt. interrupt)
*/
r5_status = readl(cygaud->audio + INTH_R5F_STATUS_OFFSET);
if (!(r5_status & (ANY_PLAYBACK_IRQ | ANY_CAPTURE_IRQ)))
return IRQ_NONE;
/* If playback interrupt happened */
if (ANY_PLAYBACK_IRQ & r5_status) {
handle_playback_irq(cygaud);
writel(ANY_PLAYBACK_IRQ & r5_status,
cygaud->audio + INTH_R5F_CLEAR_OFFSET);
}
/* If capture interrupt happened */
if (ANY_CAPTURE_IRQ & r5_status) {
handle_capture_irq(cygaud);
writel(ANY_CAPTURE_IRQ & r5_status,
cygaud->audio + INTH_R5F_CLEAR_OFFSET);
}
return IRQ_HANDLED;
}
static int cygnus_pcm_open(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
struct cygnus_aio_port *aio;
int ret;
aio = cygnus_dai_get_dma_data(substream);
if (!aio)
return -ENODEV;
dev_dbg(rtd->cpu_dai->dev, "%s port %d\n", __func__, aio->portnum);
snd_soc_set_runtime_hwparams(substream, &cygnus_pcm_hw);
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, PERIOD_BYTES_MIN);
if (ret < 0)
return ret;
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, PERIOD_BYTES_MIN);
if (ret < 0)
return ret;
/*
* Keep track of which substream belongs to which port.
* This info is needed by snd_pcm_period_elapsed() in irq_handler
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aio->play_stream = substream;
else
aio->capture_stream = substream;
return 0;
}
static int cygnus_pcm_close(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct cygnus_aio_port *aio;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(rtd->cpu_dai->dev, "%s port %d\n", __func__, aio->portnum);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
aio->play_stream = NULL;
else
aio->capture_stream = NULL;
if (!aio->play_stream && !aio->capture_stream)
dev_dbg(rtd->cpu_dai->dev, "freed port %d\n", aio->portnum);
return 0;
}
static int cygnus_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
struct cygnus_aio_port *aio;
int ret = 0;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(rtd->cpu_dai->dev, "%s port %d\n", __func__, aio->portnum);
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
runtime->dma_bytes = params_buffer_bytes(params);
return ret;
}
static int cygnus_pcm_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct cygnus_aio_port *aio;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(rtd->cpu_dai->dev, "%s port %d\n", __func__, aio->portnum);
snd_pcm_set_runtime_buffer(substream, NULL);
return 0;
}
static int cygnus_pcm_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
struct cygnus_aio_port *aio;
unsigned long bufsize, periodsize;
int ret = 0;
bool is_play;
u32 start;
struct ringbuf_regs *p_rbuf = NULL;
aio = cygnus_dai_get_dma_data(substream);
dev_dbg(rtd->cpu_dai->dev, "%s port %d\n", __func__, aio->portnum);
bufsize = snd_pcm_lib_buffer_bytes(substream);
periodsize = snd_pcm_lib_period_bytes(substream);
dev_dbg(rtd->cpu_dai->dev, "%s (buf_size %lu) (period_size %lu)\n",
__func__, bufsize, periodsize);
configure_ringbuf_regs(substream);
p_rbuf = get_ringbuf(substream);
start = runtime->dma_addr;
is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1 : 0;
ringbuf_set_initial(aio->cygaud->audio, p_rbuf, is_play, start,
periodsize, bufsize);
return ret;
}
static snd_pcm_uframes_t cygnus_pcm_pointer(struct snd_pcm_substream *substream)
{
struct cygnus_aio_port *aio;
unsigned int res = 0, cur = 0, base = 0;
struct ringbuf_regs *p_rbuf = NULL;
aio = cygnus_dai_get_dma_data(substream);
/*
* Get the offset of the current read (for playack) or write
* index (for capture). Report this value back to the asoc framework.
*/
p_rbuf = get_ringbuf(substream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
cur = readl(aio->cygaud->audio + p_rbuf->rdaddr);
else
cur = readl(aio->cygaud->audio + p_rbuf->wraddr);
base = readl(aio->cygaud->audio + p_rbuf->baseaddr);
/*
* Mask off the MSB of the rdaddr,wraddr and baseaddr
* since MSB is not part of the address
*/
res = (cur & 0x7fffffff) - (base & 0x7fffffff);
return bytes_to_frames(substream->runtime, res);
}
static int cygnus_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
{
struct snd_pcm_substream *substream = pcm->streams[stream].substream;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_dma_buffer *buf = &substream->dma_buffer;
size_t size;
size = cygnus_pcm_hw.buffer_bytes_max;
buf->dev.type = SNDRV_DMA_TYPE_DEV;
buf->dev.dev = pcm->card->dev;
buf->private_data = NULL;
buf->area = dma_alloc_coherent(pcm->card->dev, size,
&buf->addr, GFP_KERNEL);
dev_dbg(rtd->cpu_dai->dev, "%s: size 0x%zx @ %pK\n",
__func__, size, buf->area);
if (!buf->area) {
dev_err(rtd->cpu_dai->dev, "%s: dma_alloc failed\n", __func__);
return -ENOMEM;
}
buf->bytes = size;
return 0;
}
static const struct snd_pcm_ops cygnus_pcm_ops = {
.open = cygnus_pcm_open,
.close = cygnus_pcm_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = cygnus_pcm_hw_params,
.hw_free = cygnus_pcm_hw_free,
.prepare = cygnus_pcm_prepare,
.trigger = cygnus_pcm_trigger,
.pointer = cygnus_pcm_pointer,
};
static void cygnus_dma_free_dma_buffers(struct snd_pcm *pcm)
{
struct snd_pcm_substream *substream;
struct snd_dma_buffer *buf;
substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
if (substream) {
buf = &substream->dma_buffer;
if (buf->area) {
dma_free_coherent(pcm->card->dev, buf->bytes,
buf->area, buf->addr);
buf->area = NULL;
}
}
substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
if (substream) {
buf = &substream->dma_buffer;
if (buf->area) {
dma_free_coherent(pcm->card->dev, buf->bytes,
buf->area, buf->addr);
buf->area = NULL;
}
}
}
static int cygnus_dma_new(struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
int ret;
if (!card->dev->dma_mask)
card->dev->dma_mask = &cygnus_dma_dmamask;
if (!card->dev->coherent_dma_mask)
card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
ret = cygnus_pcm_preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_PLAYBACK);
if (ret)
return ret;
}
if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
ret = cygnus_pcm_preallocate_dma_buffer(pcm,
SNDRV_PCM_STREAM_CAPTURE);
if (ret) {
cygnus_dma_free_dma_buffers(pcm);
return ret;
}
}
return 0;
}
static struct snd_soc_platform_driver cygnus_soc_platform = {
.ops = &cygnus_pcm_ops,
.pcm_new = cygnus_dma_new,
.pcm_free = cygnus_dma_free_dma_buffers,
};
int cygnus_soc_platform_register(struct device *dev,
struct cygnus_audio *cygaud)
{
int rc = 0;
dev_dbg(dev, "%s Enter\n", __func__);
rc = devm_request_irq(dev, cygaud->irq_num, cygnus_dma_irq,
IRQF_SHARED, "cygnus-audio", cygaud);
if (rc) {
dev_err(dev, "%s request_irq error %d\n", __func__, rc);
return rc;
}
rc = snd_soc_register_platform(dev, &cygnus_soc_platform);
if (rc) {
dev_err(dev, "%s failed\n", __func__);
return rc;
}
return 0;
}
int cygnus_soc_platform_unregister(struct device *dev)
{
snd_soc_unregister_platform(dev);
return 0;
}
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Cygnus ASoC PCM module");

1529
sound/soc/bcm/cygnus-ssp.c Normal file
View File

File diff suppressed because it is too large Load Diff

139
sound/soc/bcm/cygnus-ssp.h Normal file
View File

@@ -0,0 +1,139 @@
/*
* Copyright (C) 2014-2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __CYGNUS_SSP_H__
#define __CYGNUS_SSP_H__
#define CYGNUS_TDM_DAI_MAX_SLOTS 16
#define CYGNUS_MAX_PLAYBACK_PORTS 4
#define CYGNUS_MAX_CAPTURE_PORTS 3
#define CYGNUS_MAX_I2S_PORTS 3
#define CYGNUS_MAX_PORTS CYGNUS_MAX_PLAYBACK_PORTS
#define CYGNUS_AUIDO_MAX_NUM_CLKS 3
#define CYGNUS_SSP_FRAMEBITS_DIV 1
#define CYGNUS_SSPMODE_I2S 0
#define CYGNUS_SSPMODE_TDM 1
#define CYGNUS_SSPMODE_UNKNOWN -1
#define CYGNUS_SSP_CLKSRC_PLL 0
/* Max string length of our dt property names */
#define PROP_LEN_MAX 40
struct ringbuf_regs {
unsigned rdaddr;
unsigned wraddr;
unsigned baseaddr;
unsigned endaddr;
unsigned fmark; /* freemark for play, fullmark for caputure */
unsigned period_bytes;
unsigned buf_size;
};
#define RINGBUF_REG_PLAYBACK(num) ((struct ringbuf_regs) { \
.rdaddr = SRC_RBUF_ ##num## _RDADDR_OFFSET, \
.wraddr = SRC_RBUF_ ##num## _WRADDR_OFFSET, \
.baseaddr = SRC_RBUF_ ##num## _BASEADDR_OFFSET, \
.endaddr = SRC_RBUF_ ##num## _ENDADDR_OFFSET, \
.fmark = SRC_RBUF_ ##num## _FREE_MARK_OFFSET, \
.period_bytes = 0, \
.buf_size = 0, \
})
#define RINGBUF_REG_CAPTURE(num) ((struct ringbuf_regs) { \
.rdaddr = DST_RBUF_ ##num## _RDADDR_OFFSET, \
.wraddr = DST_RBUF_ ##num## _WRADDR_OFFSET, \
.baseaddr = DST_RBUF_ ##num## _BASEADDR_OFFSET, \
.endaddr = DST_RBUF_ ##num## _ENDADDR_OFFSET, \
.fmark = DST_RBUF_ ##num## _FULL_MARK_OFFSET, \
.period_bytes = 0, \
.buf_size = 0, \
})
enum cygnus_audio_port_type {
PORT_TDM,
PORT_SPDIF,
};
struct cygnus_ssp_regs {
u32 i2s_stream_cfg;
u32 i2s_cfg;
u32 i2s_cap_stream_cfg;
u32 i2s_cap_cfg;
u32 i2s_mclk_cfg;
u32 bf_destch_ctrl;
u32 bf_destch_cfg;
u32 bf_sourcech_ctrl;
u32 bf_sourcech_cfg;
u32 bf_sourcech_grp;
};
struct cygnus_track_clk {
bool cap_en;
bool play_en;
bool cap_clk_en;
bool play_clk_en;
};
struct cygnus_aio_port {
int portnum;
int mode;
bool is_slave;
int streams_on; /* will be 0 if both capture and play are off */
int fsync_width;
int port_type;
u32 mclk;
u32 lrclk;
u32 bit_per_frame;
u32 pll_clk_num;
struct cygnus_audio *cygaud;
struct cygnus_ssp_regs regs;
struct ringbuf_regs play_rb_regs;
struct ringbuf_regs capture_rb_regs;
struct snd_pcm_substream *play_stream;
struct snd_pcm_substream *capture_stream;
struct cygnus_track_clk clk_trace;
};
struct cygnus_audio {
struct cygnus_aio_port portinfo[CYGNUS_MAX_PORTS];
int irq_num;
void __iomem *audio;
struct device *dev;
void __iomem *i2s_in;
struct clk *audio_clk[CYGNUS_AUIDO_MAX_NUM_CLKS];
int active_ports;
unsigned long vco_rate;
};
extern int cygnus_ssp_get_mode(struct snd_soc_dai *cpu_dai);
extern int cygnus_ssp_add_pll_tweak_controls(struct snd_soc_pcm_runtime *rtd);
extern int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai,
int len);
extern int cygnus_soc_platform_register(struct device *dev,
struct cygnus_audio *cygaud);
extern int cygnus_soc_platform_unregister(struct device *dev);
extern int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai,
int len);
#endif

6
sound/soc/codecs/Kconfig
View File

@@ -59,6 +59,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_CS42XX8_I2C if I2C select SND_SOC_CS42XX8_I2C if I2C
select SND_SOC_CS4349 if I2C select SND_SOC_CS4349 if I2C
select SND_SOC_CS47L24 if MFD_CS47L24 select SND_SOC_CS47L24 if MFD_CS47L24
select SND_SOC_CS53L30 if I2C
select SND_SOC_CX20442 if TTY select SND_SOC_CX20442 if TTY
select SND_SOC_DA7210 if SND_SOC_I2C_AND_SPI select SND_SOC_DA7210 if SND_SOC_I2C_AND_SPI
select SND_SOC_DA7213 if I2C select SND_SOC_DA7213 if I2C
@@ -464,6 +465,11 @@ config SND_SOC_CS4349
config SND_SOC_CS47L24 config SND_SOC_CS47L24
tristate tristate
# Cirrus Logic Quad-Channel ADC
config SND_SOC_CS53L30
tristate "Cirrus Logic CS53L30 CODEC"
depends on I2C
config SND_SOC_CX20442 config SND_SOC_CX20442
tristate tristate
depends on TTY depends on TTY

2
sound/soc/codecs/Makefile
View File

@@ -52,6 +52,7 @@ snd-soc-cs42xx8-objs := cs42xx8.o
snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o
snd-soc-cs4349-objs := cs4349.o snd-soc-cs4349-objs := cs4349.o
snd-soc-cs47l24-objs := cs47l24.o snd-soc-cs47l24-objs := cs47l24.o
snd-soc-cs53l30-objs := cs53l30.o
snd-soc-cx20442-objs := cx20442.o snd-soc-cx20442-objs := cx20442.o
snd-soc-da7210-objs := da7210.o snd-soc-da7210-objs := da7210.o
snd-soc-da7213-objs := da7213.o snd-soc-da7213-objs := da7213.o
@@ -270,6 +271,7 @@ obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o
obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o
obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o
obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o
obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o
obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o

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sound/soc/codecs/cs53l30.c Normal file
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/*
* ALSA SoC CS53L30 codec driver
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Author: Paul Handrigan <Paul.Handrigan@cirrus.com>,
* Tim Howe <Tim.Howe@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __CS53L30_H__
#define __CS53L30_H__
/* I2C Registers */
#define CS53L30_DEVID_AB 0x01 /* Device ID A & B [RO]. */
#define CS53L30_DEVID_CD 0x02 /* Device ID C & D [RO]. */
#define CS53L30_DEVID_E 0x03 /* Device ID E [RO]. */
#define CS53L30_REVID 0x05 /* Revision ID [RO]. */
#define CS53L30_PWRCTL 0x06 /* Power Control. */
#define CS53L30_MCLKCTL 0x07 /* MCLK Control. */
#define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */
#define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */
#define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */
#define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */
#define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */
#define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */
#define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */
#define CS53L30_ASP_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */
#define CS53L30_ASP_TDMTX_EN1 0x12 /* ASP1 TDM TX Enable 1 */
#define CS53L30_ASP_TDMTX_EN2 0x13 /* ASP1 TDM TX Enable 2 */
#define CS53L30_ASP_TDMTX_EN3 0x14 /* ASP1 TDM TX Enable 3 */
#define CS53L30_ASP_TDMTX_EN4 0x15 /* ASP1 TDM TX Enable 4 */
#define CS53L30_ASP_TDMTX_EN5 0x16 /* ASP1 TDM TX Enable 5 */
#define CS53L30_ASP_TDMTX_EN6 0x17 /* ASP1 TDM TX Enable 6 */
#define CS53L30_ASP_CTL2 0x18 /* ASP2 Control. */
#define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */
#define CS53L30_LRCK_CTL1 0x1B /* LRCK Control 1. */
#define CS53L30_LRCK_CTL2 0x1C /* LRCK Control 2. */
#define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */
#define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */
#define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */
#define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */
#define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */
#define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */
#define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */
#define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */
#define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */
#define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */
#define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */
#define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */
#define CS53L30_ADC1A_DIG_VOL 0x2B /* ADC1A Digital Volume. */
#define CS53L30_ADC1B_DIG_VOL 0x2C /* ADC1B Digital Volume. */
#define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */
#define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */
#define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */
#define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */
#define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */
#define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */
#define CS53L30_ADC2A_DIG_VOL 0x33 /* ADC2A Digital Volume. */
#define CS53L30_ADC2B_DIG_VOL 0x34 /* ADC2B Digital Volume. */
#define CS53L30_INT_MASK 0x35 /* Interrupt Mask. */
#define CS53L30_IS 0x36 /* Interrupt Status. */
#define CS53L30_MAX_REGISTER 0x36
#define CS53L30_TDM_SLOT_MAX 4
#define CS53L30_ASP_TDMTX_CTL(x) (CS53L30_ASP_TDMTX_CTL1 + (x))
/* x : index for registers; n : index for slot; 8 slots per register */
#define CS53L30_ASP_TDMTX_ENx(x) (CS53L30_ASP_TDMTX_EN6 - (x))
#define CS53L30_ASP_TDMTX_ENn(n) CS53L30_ASP_TDMTX_ENx((n) >> 3)
#define CS53L30_ASP_TDMTX_ENx_MAX 6
/* Device ID */
#define CS53L30_DEVID 0x53A30
/* PDN_DONE Poll Maximum
* If soft ramp is set it will take much longer to power down
* the system.
*/
#define CS53L30_PDN_POLL_MAX 90
/* Bitfield Definitions */
/* R6 (0x06) CS53L30_PWRCTL - Power Control */
#define CS53L30_PDN_ULP_SHIFT 7
#define CS53L30_PDN_ULP_MASK (1 << CS53L30_PDN_ULP_SHIFT)
#define CS53L30_PDN_ULP (1 << CS53L30_PDN_ULP_SHIFT)
#define CS53L30_PDN_LP_SHIFT 6
#define CS53L30_PDN_LP_MASK (1 << CS53L30_PDN_LP_SHIFT)
#define CS53L30_PDN_LP (1 << CS53L30_PDN_LP_SHIFT)
#define CS53L30_DISCHARGE_FILT_SHIFT 5
#define CS53L30_DISCHARGE_FILT_MASK (1 << CS53L30_DISCHARGE_FILT_SHIFT)
#define CS53L30_DISCHARGE_FILT (1 << CS53L30_DISCHARGE_FILT_SHIFT)
#define CS53L30_THMS_PDN_SHIFT 4
#define CS53L30_THMS_PDN_MASK (1 << CS53L30_THMS_PDN_SHIFT)
#define CS53L30_THMS_PDN (1 << CS53L30_THMS_PDN_SHIFT)
#define CS53L30_PWRCTL_DEFAULT (CS53L30_THMS_PDN)
/* R7 (0x07) CS53L30_MCLKCTL - MCLK Control */
#define CS53L30_MCLK_DIS_SHIFT 7
#define CS53L30_MCLK_DIS_MASK (1 << CS53L30_MCLK_DIS_SHIFT)
#define CS53L30_MCLK_DIS (1 << CS53L30_MCLK_DIS_SHIFT)
#define CS53L30_MCLK_INT_SCALE_SHIFT 6
#define CS53L30_MCLK_INT_SCALE_MASK (1 << CS53L30_MCLK_INT_SCALE_SHIFT)
#define CS53L30_MCLK_INT_SCALE (1 << CS53L30_MCLK_INT_SCALE_SHIFT)
#define CS53L30_DMIC_DRIVE_SHIFT 5
#define CS53L30_DMIC_DRIVE_MASK (1 << CS53L30_DMIC_DRIVE_SHIFT)
#define CS53L30_DMIC_DRIVE (1 << CS53L30_DMIC_DRIVE_SHIFT)
#define CS53L30_MCLK_DIV_SHIFT 2
#define CS53L30_MCLK_DIV_WIDTH 2
#define CS53L30_MCLK_DIV_MASK (((1 << CS53L30_MCLK_DIV_WIDTH) - 1) << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_MCLK_DIV_BY_1 (0x0 << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_MCLK_DIV_BY_2 (0x1 << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_MCLK_DIV_BY_3 (0x2 << CS53L30_MCLK_DIV_SHIFT)
#define CS53L30_SYNC_EN_SHIFT 1
#define CS53L30_SYNC_EN_MASK (1 << CS53L30_SYNC_EN_SHIFT)
#define CS53L30_SYNC_EN (1 << CS53L30_SYNC_EN_SHIFT)
#define CS53L30_MCLKCTL_DEFAULT (CS53L30_MCLK_DIV_BY_2)
/* R8 (0x08) CS53L30_INT_SR_CTL - Internal Sample Rate Control */
#define CS53L30_INTRNL_FS_RATIO_SHIFT 4
#define CS53L30_INTRNL_FS_RATIO_MASK (1 << CS53L30_INTRNL_FS_RATIO_SHIFT)
#define CS53L30_INTRNL_FS_RATIO (1 << CS53L30_INTRNL_FS_RATIO_SHIFT)
#define CS53L30_MCLK_19MHZ_EN_SHIFT 0
#define CS53L30_MCLK_19MHZ_EN_MASK (1 << CS53L30_MCLK_19MHZ_EN_SHIFT)
#define CS53L30_MCLK_19MHZ_EN (1 << CS53L30_MCLK_19MHZ_EN_SHIFT)
/* 0x6 << 1 is reserved bits */
#define CS53L30_INT_SR_CTL_DEFAULT (CS53L30_INTRNL_FS_RATIO | 0x6 << 1)
/* R10 (0x0A) CS53L30_MICBIAS_CTL - Mic Bias Control */
#define CS53L30_MIC4_BIAS_PDN_SHIFT 7
#define CS53L30_MIC4_BIAS_PDN_MASK (1 << CS53L30_MIC4_BIAS_PDN_SHIFT)
#define CS53L30_MIC4_BIAS_PDN (1 << CS53L30_MIC4_BIAS_PDN_SHIFT)
#define CS53L30_MIC3_BIAS_PDN_SHIFT 6
#define CS53L30_MIC3_BIAS_PDN_MASK (1 << CS53L30_MIC3_BIAS_PDN_SHIFT)
#define CS53L30_MIC3_BIAS_PDN (1 << CS53L30_MIC3_BIAS_PDN_SHIFT)
#define CS53L30_MIC2_BIAS_PDN_SHIFT 5
#define CS53L30_MIC2_BIAS_PDN_MASK (1 << CS53L30_MIC2_BIAS_PDN_SHIFT)
#define CS53L30_MIC2_BIAS_PDN (1 << CS53L30_MIC2_BIAS_PDN_SHIFT)
#define CS53L30_MIC1_BIAS_PDN_SHIFT 4
#define CS53L30_MIC1_BIAS_PDN_MASK (1 << CS53L30_MIC1_BIAS_PDN_SHIFT)
#define CS53L30_MIC1_BIAS_PDN (1 << CS53L30_MIC1_BIAS_PDN_SHIFT)
#define CS53L30_MICx_BIAS_PDN (0xf << CS53L30_MIC1_BIAS_PDN_SHIFT)
#define CS53L30_VP_MIN_SHIFT 2
#define CS53L30_VP_MIN_MASK (1 << CS53L30_VP_MIN_SHIFT)
#define CS53L30_VP_MIN (1 << CS53L30_VP_MIN_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_SHIFT 0
#define CS53L30_MIC_BIAS_CTRL_WIDTH 2
#define CS53L30_MIC_BIAS_CTRL_MASK (((1 << CS53L30_MIC_BIAS_CTRL_WIDTH) - 1) << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_HIZ (0 << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_1V8 (1 << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MIC_BIAS_CTRL_2V75 (2 << CS53L30_MIC_BIAS_CTRL_SHIFT)
#define CS53L30_MICBIAS_CTL_DEFAULT (CS53L30_MICx_BIAS_PDN | CS53L30_VP_MIN)
/* R12 (0x0C) CS53L30_ASPCFG_CTL - ASP Configuration Control */
#define CS53L30_ASP_MS_SHIFT 7
#define CS53L30_ASP_MS_MASK (1 << CS53L30_ASP_MS_SHIFT)
#define CS53L30_ASP_MS (1 << CS53L30_ASP_MS_SHIFT)
#define CS53L30_ASP_SCLK_INV_SHIFT 4
#define CS53L30_ASP_SCLK_INV_MASK (1 << CS53L30_ASP_SCLK_INV_SHIFT)
#define CS53L30_ASP_SCLK_INV (1 << CS53L30_ASP_SCLK_INV_SHIFT)
#define CS53L30_ASP_RATE_SHIFT 0
#define CS53L30_ASP_RATE_WIDTH 4
#define CS53L30_ASP_RATE_MASK (((1 << CS53L30_ASP_RATE_WIDTH) - 1) << CS53L30_ASP_RATE_SHIFT)
#define CS53L30_ASP_RATE_48K (0xc << CS53L30_ASP_RATE_SHIFT)
#define CS53L30_ASPCFG_CTL_DEFAULT (CS53L30_ASP_RATE_48K)
/* R13/R24 (0x0D/0x18) CS53L30_ASP_CTL1 & CS53L30_ASP_CTL2 - ASP Control 1~2 */
#define CS53L30_ASP_TDM_PDN_SHIFT 7
#define CS53L30_ASP_TDM_PDN_MASK (1 << CS53L30_ASP_TDM_PDN_SHIFT)
#define CS53L30_ASP_TDM_PDN (1 << CS53L30_ASP_TDM_PDN_SHIFT)
#define CS53L30_ASP_SDOUTx_PDN_SHIFT 6
#define CS53L30_ASP_SDOUTx_PDN_MASK (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT)
#define CS53L30_ASP_SDOUTx_PDN (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT)
#define CS53L30_ASP_3ST_SHIFT 5
#define CS53L30_ASP_3ST_MASK (1 << CS53L30_ASP_3ST_SHIFT)
#define CS53L30_ASP_3ST (1 << CS53L30_ASP_3ST_SHIFT)
#define CS53L30_SHIFT_LEFT_SHIFT 4
#define CS53L30_SHIFT_LEFT_MASK (1 << CS53L30_SHIFT_LEFT_SHIFT)
#define CS53L30_SHIFT_LEFT (1 << CS53L30_SHIFT_LEFT_SHIFT)
#define CS53L30_ASP_SDOUTx_DRIVE_SHIFT 0
#define CS53L30_ASP_SDOUTx_DRIVE_MASK (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT)
#define CS53L30_ASP_SDOUTx_DRIVE (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT)
#define CS53L30_ASP_CTL1_DEFAULT (CS53L30_ASP_TDM_PDN)
#define CS53L30_ASP_CTL2_DEFAULT (0)
/* R14 (0x0E) ~ R17 (0x11) CS53L30_ASP_TDMTX_CTLx - ASP TDM TX Control 1~4 */
#define CS53L30_ASP_CHx_TX_STATE_SHIFT 7
#define CS53L30_ASP_CHx_TX_STATE_MASK (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT)
#define CS53L30_ASP_CHx_TX_STATE (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT)
#define CS53L30_ASP_CHx_TX_LOC_SHIFT 0
#define CS53L30_ASP_CHx_TX_LOC_WIDTH 6
#define CS53L30_ASP_CHx_TX_LOC_MASK (((1 << CS53L30_ASP_CHx_TX_LOC_WIDTH) - 1) << CS53L30_ASP_CHx_TX_LOC_SHIFT)
#define CS53L30_ASP_CHx_TX_LOC_MAX (47 << CS53L30_ASP_CHx_TX_LOC_SHIFT)
#define CS53L30_ASP_CHx_TX_LOC(x) ((x) << CS53L30_ASP_CHx_TX_LOC_SHIFT)
#define CS53L30_ASP_TDMTX_CTLx_DEFAULT (CS53L30_ASP_CHx_TX_LOC_MAX)
/* R18 (0x12) ~ R23 (0x17) CS53L30_ASP_TDMTX_ENx - ASP TDM TX Enable 1~6 */
#define CS53L30_ASP_TDMTX_ENx_DEFAULT (0)
/* R26 (0x1A) CS53L30_SFT_RAMP - Soft Ramp Control */
#define CS53L30_DIGSFT_SHIFT 5
#define CS53L30_DIGSFT_MASK (1 << CS53L30_DIGSFT_SHIFT)
#define CS53L30_DIGSFT (1 << CS53L30_DIGSFT_SHIFT)
#define CS53L30_SFT_RMP_DEFAULT (0)
/* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */
#define CS53L30_LRCK_50_NPW_SHIFT 3
#define CS53L30_LRCK_50_NPW_MASK (1 << CS53L30_LRCK_50_NPW_SHIFT)
#define CS53L30_LRCK_50_NPW (1 << CS53L30_LRCK_50_NPW_SHIFT)
#define CS53L30_LRCK_TPWH_SHIFT 0
#define CS53L30_LRCK_TPWH_WIDTH 3
#define CS53L30_LRCK_TPWH_MASK (((1 << CS53L30_LRCK_TPWH_WIDTH) - 1) << CS53L30_LRCK_TPWH_SHIFT)
#define CS53L30_LRCK_TPWH(x) (((x) << CS53L30_LRCK_TPWH_SHIFT) & CS53L30_LRCK_TPWH_MASK)
#define CS53L30_LRCK_CTLx_DEFAULT (0)
/* R31 (0x1F) CS53L30_MUTEP_CTL1 - MUTE Pin Control 1 */
#define CS53L30_MUTE_PDN_ULP_SHIFT 7
#define CS53L30_MUTE_PDN_ULP_MASK (1 << CS53L30_MUTE_PDN_ULP_SHIFT)
#define CS53L30_MUTE_PDN_ULP (1 << CS53L30_MUTE_PDN_ULP_SHIFT)
#define CS53L30_MUTE_PDN_LP_SHIFT 6
#define CS53L30_MUTE_PDN_LP_MASK (1 << CS53L30_MUTE_PDN_LP_SHIFT)
#define CS53L30_MUTE_PDN_LP (1 << CS53L30_MUTE_PDN_LP_SHIFT)
#define CS53L30_MUTE_M4B_PDN_SHIFT 4
#define CS53L30_MUTE_M4B_PDN_MASK (1 << CS53L30_MUTE_M4B_PDN_SHIFT)
#define CS53L30_MUTE_M4B_PDN (1 << CS53L30_MUTE_M4B_PDN_SHIFT)
#define CS53L30_MUTE_M3B_PDN_SHIFT 3
#define CS53L30_MUTE_M3B_PDN_MASK (1 << CS53L30_MUTE_M3B_PDN_SHIFT)
#define CS53L30_MUTE_M3B_PDN (1 << CS53L30_MUTE_M3B_PDN_SHIFT)
#define CS53L30_MUTE_M2B_PDN_SHIFT 2
#define CS53L30_MUTE_M2B_PDN_MASK (1 << CS53L30_MUTE_M2B_PDN_SHIFT)
#define CS53L30_MUTE_M2B_PDN (1 << CS53L30_MUTE_M2B_PDN_SHIFT)
#define CS53L30_MUTE_M1B_PDN_SHIFT 1
#define CS53L30_MUTE_M1B_PDN_MASK (1 << CS53L30_MUTE_M1B_PDN_SHIFT)
#define CS53L30_MUTE_M1B_PDN (1 << CS53L30_MUTE_M1B_PDN_SHIFT)
/* Note: be careful - x starts from 0 */
#define CS53L30_MUTE_MxB_PDN_SHIFT(x) (CS53L30_MUTE_M1B_PDN_SHIFT + (x))
#define CS53L30_MUTE_MxB_PDN_MASK(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x))
#define CS53L30_MUTE_MxB_PDN(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x))
#define CS53L30_MUTE_MB_ALL_PDN_SHIFT 0
#define CS53L30_MUTE_MB_ALL_PDN_MASK (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT)
#define CS53L30_MUTE_MB_ALL_PDN (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT)
#define CS53L30_MUTEP_CTL1_MUTEALL (0xdf)
#define CS53L30_MUTEP_CTL1_DEFAULT (0)
/* R32 (0x20) CS53L30_MUTEP_CTL2 - MUTE Pin Control 2 */
#define CS53L30_MUTE_PIN_POLARITY_SHIFT 7
#define CS53L30_MUTE_PIN_POLARITY_MASK (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT)
#define CS53L30_MUTE_PIN_POLARITY (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT)
#define CS53L30_MUTE_ASP_TDM_PDN_SHIFT 6
#define CS53L30_MUTE_ASP_TDM_PDN_MASK (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT)
#define CS53L30_MUTE_ASP_TDM_PDN (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT 5
#define CS53L30_MUTE_ASP_SDOUT2_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT2_PDN (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT 4
#define CS53L30_MUTE_ASP_SDOUT1_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUT1_PDN (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT)
/* Note: be careful - x starts from 0 */
#define CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x) ((x) + CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT)
#define CS53L30_MUTE_ASP_SDOUTx_PDN_MASK(x) (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x))
#define CS53L30_MUTE_ASP_SDOUTx_PDN (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x))
#define CS53L30_MUTE_ADC2B_PDN_SHIFT 3
#define CS53L30_MUTE_ADC2B_PDN_MASK (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT)
#define CS53L30_MUTE_ADC2B_PDN (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT)
#define CS53L30_MUTE_ADC2A_PDN_SHIFT 2
#define CS53L30_MUTE_ADC2A_PDN_MASK (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT)
#define CS53L30_MUTE_ADC2A_PDN (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT)
#define CS53L30_MUTE_ADC1B_PDN_SHIFT 1
#define CS53L30_MUTE_ADC1B_PDN_MASK (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT)
#define CS53L30_MUTE_ADC1B_PDN (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT)
#define CS53L30_MUTE_ADC1A_PDN_SHIFT 0
#define CS53L30_MUTE_ADC1A_PDN_MASK (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT)
#define CS53L30_MUTE_ADC1A_PDN (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT)
#define CS53L30_MUTEP_CTL2_DEFAULT (CS53L30_MUTE_PIN_POLARITY)
/* R33 (0x21) CS53L30_INBIAS_CTL1 - Input Bias Control 1 */
#define CS53L30_IN4M_BIAS_SHIFT 6
#define CS53L30_IN4M_BIAS_WIDTH 2
#define CS53L30_IN4M_BIAS_MASK (((1 << CS53L30_IN4M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4M_BIAS_OPEN (0 << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4M_BIAS_PULL_DOWN (1 << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4M_BIAS_VCM (2 << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_SHIFT 4
#define CS53L30_IN4P_BIAS_WIDTH 2
#define CS53L30_IN4P_BIAS_MASK (((1 << CS53L30_IN4P_BIAS_WIDTH) - 1) << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_OPEN (0 << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_PULL_DOWN (1 << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN4P_BIAS_VCM (2 << CS53L30_IN4P_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_SHIFT 2
#define CS53L30_IN3M_BIAS_WIDTH 2
#define CS53L30_IN3M_BIAS_MASK (((1 << CS53L30_IN3M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_OPEN (0 << CS53L30_IN3M_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_PULL_DOWN (1 << CS53L30_IN3M_BIAS_SHIFT)
#define CS53L30_IN3M_BIAS_VCM (2 << CS53L30_IN3M_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_SHIFT 0
#define CS53L30_IN3P_BIAS_WIDTH 2
#define CS53L30_IN3P_BIAS_MASK (((1 << CS53L30_IN3P_BIAS_WIDTH) - 1) << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_OPEN (0 << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_PULL_DOWN (1 << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_IN3P_BIAS_VCM (2 << CS53L30_IN3P_BIAS_SHIFT)
#define CS53L30_INBIAS_CTL1_DEFAULT (CS53L30_IN4M_BIAS_VCM | CS53L30_IN4P_BIAS_VCM |\
CS53L30_IN3M_BIAS_VCM | CS53L30_IN3P_BIAS_VCM)
/* R34 (0x22) CS53L30_INBIAS_CTL2 - Input Bias Control 2 */
#define CS53L30_IN2M_BIAS_SHIFT 6
#define CS53L30_IN2M_BIAS_WIDTH 2
#define CS53L30_IN2M_BIAS_MASK (((1 << CS53L30_IN2M_BIAS_WIDTH) - 1) << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2M_BIAS_OPEN (0 << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2M_BIAS_PULL_DOWN (1 << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2M_BIAS_VCM (2 << CS53L30_IN2M_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_SHIFT 4
#define CS53L30_IN2P_BIAS_WIDTH 2
#define CS53L30_IN2P_BIAS_MASK (((1 << CS53L30_IN2P_BIAS_WIDTH) - 1) << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_OPEN (0 << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_PULL_DOWN (1 << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN2P_BIAS_VCM (2 << CS53L30_IN2P_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_SHIFT 2
#define CS53L30_IN1M_BIAS_WIDTH 2
#define CS53L30_IN1M_BIAS_MASK (((1 << CS53L30_IN1M_BIAS_WIDTH) - 1) << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_OPEN (0 << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_PULL_DOWN (1 << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1M_BIAS_VCM (2 << CS53L30_IN1M_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_SHIFT 0
#define CS53L30_IN1P_BIAS_WIDTH 2
#define CS53L30_IN1P_BIAS_MASK (((1 << CS53L30_IN1P_BIAS_WIDTH) - 1) << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_OPEN (0 << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_PULL_DOWN (1 << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_IN1P_BIAS_VCM (2 << CS53L30_IN1P_BIAS_SHIFT)
#define CS53L30_INBIAS_CTL2_DEFAULT (CS53L30_IN2M_BIAS_VCM | CS53L30_IN2P_BIAS_VCM |\
CS53L30_IN1M_BIAS_VCM | CS53L30_IN1P_BIAS_VCM)
/* R35 (0x23) & R36 (0x24) CS53L30_DMICx_STR_CTL - DMIC1 & DMIC2 Stereo Control */
#define CS53L30_DMICx_STEREO_ENB_SHIFT 5
#define CS53L30_DMICx_STEREO_ENB_MASK (1 << CS53L30_DMICx_STEREO_ENB_SHIFT)
#define CS53L30_DMICx_STEREO_ENB (1 << CS53L30_DMICx_STEREO_ENB_SHIFT)
/* 0x88 and 0xCC are reserved bits */
#define CS53L30_DMIC1_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0x88)
#define CS53L30_DMIC2_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0xCC)
/* R37/R45 (0x25/0x2D) CS53L30_ADCDMICx_CTL1 - ADC1/DMIC1 & ADC2/DMIC2 Control 1 */
#define CS53L30_ADCxB_PDN_SHIFT 7
#define CS53L30_ADCxB_PDN_MASK (1 << CS53L30_ADCxB_PDN_SHIFT)
#define CS53L30_ADCxB_PDN (1 << CS53L30_ADCxB_PDN_SHIFT)
#define CS53L30_ADCxA_PDN_SHIFT 6
#define CS53L30_ADCxA_PDN_MASK (1 << CS53L30_ADCxA_PDN_SHIFT)
#define CS53L30_ADCxA_PDN (1 << CS53L30_ADCxA_PDN_SHIFT)
#define CS53L30_DMICx_PDN_SHIFT 2
#define CS53L30_DMICx_PDN_MASK (1 << CS53L30_DMICx_PDN_SHIFT)
#define CS53L30_DMICx_PDN (1 << CS53L30_DMICx_PDN_SHIFT)
#define CS53L30_DMICx_SCLK_DIV_SHIFT 1
#define CS53L30_DMICx_SCLK_DIV_MASK (1 << CS53L30_DMICx_SCLK_DIV_SHIFT)
#define CS53L30_DMICx_SCLK_DIV (1 << CS53L30_DMICx_SCLK_DIV_SHIFT)
#define CS53L30_CH_TYPE_SHIFT 0
#define CS53L30_CH_TYPE_MASK (1 << CS53L30_CH_TYPE_SHIFT)
#define CS53L30_CH_TYPE (1 << CS53L30_CH_TYPE_SHIFT)
#define CS53L30_ADCDMICx_PDN_MASK 0xFF
#define CS53L30_ADCDMICx_CTL1_DEFAULT (CS53L30_DMICx_PDN)
/* R38/R46 (0x26/0x2E) CS53L30_ADCDMICx_CTL2 - ADC1/DMIC1 & ADC2/DMIC2 Control 2 */
#define CS53L30_ADCx_NOTCH_DIS_SHIFT 7
#define CS53L30_ADCx_NOTCH_DIS_MASK (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT)
#define CS53L30_ADCx_NOTCH_DIS (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT)
#define CS53L30_ADCxB_INV_SHIFT 5
#define CS53L30_ADCxB_INV_MASK (1 << CS53L30_ADCxB_INV_SHIFT)
#define CS53L30_ADCxB_INV (1 << CS53L30_ADCxB_INV_SHIFT)
#define CS53L30_ADCxA_INV_SHIFT 4
#define CS53L30_ADCxA_INV_MASK (1 << CS53L30_ADCxA_INV_SHIFT)
#define CS53L30_ADCxA_INV (1 << CS53L30_ADCxA_INV_SHIFT)
#define CS53L30_ADCxB_DIG_BOOST_SHIFT 1
#define CS53L30_ADCxB_DIG_BOOST_MASK (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT)
#define CS53L30_ADCxB_DIG_BOOST (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT)
#define CS53L30_ADCxA_DIG_BOOST_SHIFT 0
#define CS53L30_ADCxA_DIG_BOOST_MASK (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT)
#define CS53L30_ADCxA_DIG_BOOST (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT)
#define CS53L30_ADCDMIC1_CTL2_DEFAULT (0)
/* R39/R47 (0x27/0x2F) CS53L30_ADCx_CTL3 - ADC1/ADC2 Control 3 */
#define CS53L30_ADCx_HPF_EN_SHIFT 3
#define CS53L30_ADCx_HPF_EN_MASK (1 << CS53L30_ADCx_HPF_EN_SHIFT)
#define CS53L30_ADCx_HPF_EN (1 << CS53L30_ADCx_HPF_EN_SHIFT)
#define CS53L30_ADCx_HPF_CF_SHIFT 1
#define CS53L30_ADCx_HPF_CF_WIDTH 2
#define CS53L30_ADCx_HPF_CF_MASK (((1 << CS53L30_ADCx_HPF_CF_WIDTH) - 1) << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_1HZ86 (0 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_120HZ (1 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_235HZ (2 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_HPF_CF_466HZ (3 << CS53L30_ADCx_HPF_CF_SHIFT)
#define CS53L30_ADCx_NG_ALL_SHIFT 0
#define CS53L30_ADCx_NG_ALL_MASK (1 << CS53L30_ADCx_NG_ALL_SHIFT)
#define CS53L30_ADCx_NG_ALL (1 << CS53L30_ADCx_NG_ALL_SHIFT)
#define CS53L30_ADCx_CTL3_DEFAULT (CS53L30_ADCx_HPF_EN)
/* R40/R48 (0x28/0x30) CS53L30_ADCx_NG_CTL - ADC1/ADC2 Noise Gate Control */
#define CS53L30_ADCxB_NG_SHIFT 7
#define CS53L30_ADCxB_NG_MASK (1 << CS53L30_ADCxB_NG_SHIFT)
#define CS53L30_ADCxB_NG (1 << CS53L30_ADCxB_NG_SHIFT)
#define CS53L30_ADCxA_NG_SHIFT 6
#define CS53L30_ADCxA_NG_MASK (1 << CS53L30_ADCxA_NG_SHIFT)
#define CS53L30_ADCxA_NG (1 << CS53L30_ADCxA_NG_SHIFT)
#define CS53L30_ADCx_NG_BOOST_SHIFT 5
#define CS53L30_ADCx_NG_BOOST_MASK (1 << CS53L30_ADCx_NG_BOOST_SHIFT)
#define CS53L30_ADCx_NG_BOOST (1 << CS53L30_ADCx_NG_BOOST_SHIFT)
#define CS53L30_ADCx_NG_THRESH_SHIFT 2
#define CS53L30_ADCx_NG_THRESH_WIDTH 3
#define CS53L30_ADCx_NG_THRESH_MASK (((1 << CS53L30_ADCx_NG_THRESH_WIDTH) - 1) << CS53L30_ADCx_NG_THRESH_SHIFT)
#define CS53L30_ADCx_NG_DELAY_SHIFT 0
#define CS53L30_ADCx_NG_DELAY_WIDTH 2
#define CS53L30_ADCx_NG_DELAY_MASK (((1 << CS53L30_ADCx_NG_DELAY_WIDTH) - 1) << CS53L30_ADCx_NG_DELAY_SHIFT)
#define CS53L30_ADCx_NG_CTL_DEFAULT (0)
/* R41/R42/R49/R50 (0x29/0x2A/0x31/0x32) CS53L30_ADCxy_AFE_CTL - ADC1A/1B/2A/2B AFE Control */
#define CS53L30_ADCxy_PREAMP_SHIFT 6
#define CS53L30_ADCxy_PREAMP_WIDTH 2
#define CS53L30_ADCxy_PREAMP_MASK (((1 << CS53L30_ADCxy_PREAMP_WIDTH) - 1) << CS53L30_ADCxy_PREAMP_SHIFT)
#define CS53L30_ADCxy_PGA_VOL_SHIFT 0
#define CS53L30_ADCxy_PGA_VOL_WIDTH 6
#define CS53L30_ADCxy_PGA_VOL_MASK (((1 << CS53L30_ADCxy_PGA_VOL_WIDTH) - 1) << CS53L30_ADCxy_PGA_VOL_SHIFT)
#define CS53L30_ADCxy_AFE_CTL_DEFAULT (0)
/* R43/R44/R51/R52 (0x2B/0x2C/0x33/0x34) CS53L30_ADCxy_DIG_VOL - ADC1A/1B/2A/2B Digital Volume */
#define CS53L30_ADCxy_VOL_MUTE (0x80)
#define CS53L30_ADCxy_DIG_VOL_DEFAULT (0x0)
/* CS53L30_INT */
#define CS53L30_PDN_DONE (1 << 7)
#define CS53L30_THMS_TRIP (1 << 6)
#define CS53L30_SYNC_DONE (1 << 5)
#define CS53L30_ADC2B_OVFL (1 << 4)
#define CS53L30_ADC2A_OVFL (1 << 3)
#define CS53L30_ADC1B_OVFL (1 << 2)
#define CS53L30_ADC1A_OVFL (1 << 1)
#define CS53L30_MUTE_PIN (1 << 0)
#define CS53L30_DEVICE_INT_MASK 0xFF
#endif /* __CS53L30_H__ */

103
sound/soc/codecs/da7219-aad.c
View File

@@ -13,8 +13,8 @@
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/of_device.h> #include <linux/i2c.h>
#include <linux/of_irq.h> #include <linux/property.h>
#include <linux/pm_wakeirq.h> #include <linux/pm_wakeirq.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/delay.h> #include <linux/delay.h>
@@ -382,11 +382,11 @@ static irqreturn_t da7219_aad_irq_thread(int irq, void *data)
} }
/* /*
* DT to pdata conversion * DT/ACPI to pdata conversion
*/ */
static enum da7219_aad_micbias_pulse_lvl static enum da7219_aad_micbias_pulse_lvl
da7219_aad_of_micbias_pulse_lvl(struct snd_soc_codec *codec, u32 val) da7219_aad_fw_micbias_pulse_lvl(struct snd_soc_codec *codec, u32 val)
{ {
switch (val) { switch (val) {
case 2800: case 2800:
@@ -400,7 +400,7 @@ static enum da7219_aad_micbias_pulse_lvl
} }
static enum da7219_aad_btn_cfg static enum da7219_aad_btn_cfg
da7219_aad_of_btn_cfg(struct snd_soc_codec *codec, u32 val) da7219_aad_fw_btn_cfg(struct snd_soc_codec *codec, u32 val)
{ {
switch (val) { switch (val) {
case 2: case 2:
@@ -424,7 +424,7 @@ static enum da7219_aad_btn_cfg
} }
static enum da7219_aad_mic_det_thr static enum da7219_aad_mic_det_thr
da7219_aad_of_mic_det_thr(struct snd_soc_codec *codec, u32 val) da7219_aad_fw_mic_det_thr(struct snd_soc_codec *codec, u32 val)
{ {
switch (val) { switch (val) {
case 200: case 200:
@@ -442,7 +442,7 @@ static enum da7219_aad_mic_det_thr
} }
static enum da7219_aad_jack_ins_deb static enum da7219_aad_jack_ins_deb
da7219_aad_of_jack_ins_deb(struct snd_soc_codec *codec, u32 val) da7219_aad_fw_jack_ins_deb(struct snd_soc_codec *codec, u32 val)
{ {
switch (val) { switch (val) {
case 5: case 5:
@@ -468,7 +468,7 @@ static enum da7219_aad_jack_ins_deb
} }
static enum da7219_aad_jack_det_rate static enum da7219_aad_jack_det_rate
da7219_aad_of_jack_det_rate(struct snd_soc_codec *codec, const char *str) da7219_aad_fw_jack_det_rate(struct snd_soc_codec *codec, const char *str)
{ {
if (!strcmp(str, "32ms_64ms")) { if (!strcmp(str, "32ms_64ms")) {
return DA7219_AAD_JACK_DET_RATE_32_64MS; return DA7219_AAD_JACK_DET_RATE_32_64MS;
@@ -485,7 +485,7 @@ static enum da7219_aad_jack_det_rate
} }
static enum da7219_aad_jack_rem_deb static enum da7219_aad_jack_rem_deb
da7219_aad_of_jack_rem_deb(struct snd_soc_codec *codec, u32 val) da7219_aad_fw_jack_rem_deb(struct snd_soc_codec *codec, u32 val)
{ {
switch (val) { switch (val) {
case 1: case 1:
@@ -503,7 +503,7 @@ static enum da7219_aad_jack_rem_deb
} }
static enum da7219_aad_btn_avg static enum da7219_aad_btn_avg
da7219_aad_of_btn_avg(struct snd_soc_codec *codec, u32 val) da7219_aad_fw_btn_avg(struct snd_soc_codec *codec, u32 val)
{ {
switch (val) { switch (val) {
case 1: case 1:
@@ -521,7 +521,7 @@ static enum da7219_aad_btn_avg
} }
static enum da7219_aad_adc_1bit_rpt static enum da7219_aad_adc_1bit_rpt
da7219_aad_of_adc_1bit_rpt(struct snd_soc_codec *codec, u32 val) da7219_aad_fw_adc_1bit_rpt(struct snd_soc_codec *codec, u32 val)
{ {
switch (val) { switch (val) {
case 1: case 1:
@@ -538,97 +538,96 @@ static enum da7219_aad_adc_1bit_rpt
} }
} }
static struct da7219_aad_pdata *da7219_aad_of_to_pdata(struct snd_soc_codec *codec) static struct da7219_aad_pdata *da7219_aad_fw_to_pdata(struct snd_soc_codec *codec)
{ {
struct device_node *np = codec->dev->of_node; struct device *dev = codec->dev;
struct device_node *aad_np = of_find_node_by_name(np, "da7219_aad"); struct i2c_client *i2c = to_i2c_client(dev);
struct fwnode_handle *aad_np;
struct da7219_aad_pdata *aad_pdata; struct da7219_aad_pdata *aad_pdata;
const char *of_str; const char *fw_str;
u32 of_val32; u32 fw_val32;
aad_np = device_get_named_child_node(dev, "da7219_aad");
if (!aad_np) if (!aad_np)
return NULL; return NULL;
aad_pdata = devm_kzalloc(codec->dev, sizeof(*aad_pdata), GFP_KERNEL); aad_pdata = devm_kzalloc(codec->dev, sizeof(*aad_pdata), GFP_KERNEL);
if (!aad_pdata) if (!aad_pdata)
goto out; return NULL;
aad_pdata->irq = irq_of_parse_and_map(np, 0); aad_pdata->irq = i2c->irq;
if (of_property_read_u32(aad_np, "dlg,micbias-pulse-lvl", if (fwnode_property_read_u32(aad_np, "dlg,micbias-pulse-lvl",
&of_val32) >= 0) &fw_val32) >= 0)
aad_pdata->micbias_pulse_lvl = aad_pdata->micbias_pulse_lvl =
da7219_aad_of_micbias_pulse_lvl(codec, of_val32); da7219_aad_fw_micbias_pulse_lvl(codec, fw_val32);
else else
aad_pdata->micbias_pulse_lvl = DA7219_AAD_MICBIAS_PULSE_LVL_OFF; aad_pdata->micbias_pulse_lvl = DA7219_AAD_MICBIAS_PULSE_LVL_OFF;
if (of_property_read_u32(aad_np, "dlg,micbias-pulse-time", if (fwnode_property_read_u32(aad_np, "dlg,micbias-pulse-time",
&of_val32) >= 0) &fw_val32) >= 0)
aad_pdata->micbias_pulse_time = of_val32; aad_pdata->micbias_pulse_time = fw_val32;
if (of_property_read_u32(aad_np, "dlg,btn-cfg", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,btn-cfg", &fw_val32) >= 0)
aad_pdata->btn_cfg = da7219_aad_of_btn_cfg(codec, of_val32); aad_pdata->btn_cfg = da7219_aad_fw_btn_cfg(codec, fw_val32);
else else
aad_pdata->btn_cfg = DA7219_AAD_BTN_CFG_10MS; aad_pdata->btn_cfg = DA7219_AAD_BTN_CFG_10MS;
if (of_property_read_u32(aad_np, "dlg,mic-det-thr", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,mic-det-thr", &fw_val32) >= 0)
aad_pdata->mic_det_thr = aad_pdata->mic_det_thr =
da7219_aad_of_mic_det_thr(codec, of_val32); da7219_aad_fw_mic_det_thr(codec, fw_val32);
else else
aad_pdata->mic_det_thr = DA7219_AAD_MIC_DET_THR_500_OHMS; aad_pdata->mic_det_thr = DA7219_AAD_MIC_DET_THR_500_OHMS;
if (of_property_read_u32(aad_np, "dlg,jack-ins-deb", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,jack-ins-deb", &fw_val32) >= 0)
aad_pdata->jack_ins_deb = aad_pdata->jack_ins_deb =
da7219_aad_of_jack_ins_deb(codec, of_val32); da7219_aad_fw_jack_ins_deb(codec, fw_val32);
else else
aad_pdata->jack_ins_deb = DA7219_AAD_JACK_INS_DEB_20MS; aad_pdata->jack_ins_deb = DA7219_AAD_JACK_INS_DEB_20MS;
if (!of_property_read_string(aad_np, "dlg,jack-det-rate", &of_str)) if (!fwnode_property_read_string(aad_np, "dlg,jack-det-rate", &fw_str))
aad_pdata->jack_det_rate = aad_pdata->jack_det_rate =
da7219_aad_of_jack_det_rate(codec, of_str); da7219_aad_fw_jack_det_rate(codec, fw_str);
else else
aad_pdata->jack_det_rate = DA7219_AAD_JACK_DET_RATE_256_512MS; aad_pdata->jack_det_rate = DA7219_AAD_JACK_DET_RATE_256_512MS;
if (of_property_read_u32(aad_np, "dlg,jack-rem-deb", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,jack-rem-deb", &fw_val32) >= 0)
aad_pdata->jack_rem_deb = aad_pdata->jack_rem_deb =
da7219_aad_of_jack_rem_deb(codec, of_val32); da7219_aad_fw_jack_rem_deb(codec, fw_val32);
else else
aad_pdata->jack_rem_deb = DA7219_AAD_JACK_REM_DEB_1MS; aad_pdata->jack_rem_deb = DA7219_AAD_JACK_REM_DEB_1MS;
if (of_property_read_u32(aad_np, "dlg,a-d-btn-thr", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,a-d-btn-thr", &fw_val32) >= 0)
aad_pdata->a_d_btn_thr = (u8) of_val32; aad_pdata->a_d_btn_thr = (u8) fw_val32;
else else
aad_pdata->a_d_btn_thr = 0xA; aad_pdata->a_d_btn_thr = 0xA;
if (of_property_read_u32(aad_np, "dlg,d-b-btn-thr", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,d-b-btn-thr", &fw_val32) >= 0)
aad_pdata->d_b_btn_thr = (u8) of_val32; aad_pdata->d_b_btn_thr = (u8) fw_val32;
else else
aad_pdata->d_b_btn_thr = 0x16; aad_pdata->d_b_btn_thr = 0x16;
if (of_property_read_u32(aad_np, "dlg,b-c-btn-thr", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,b-c-btn-thr", &fw_val32) >= 0)
aad_pdata->b_c_btn_thr = (u8) of_val32; aad_pdata->b_c_btn_thr = (u8) fw_val32;
else else
aad_pdata->b_c_btn_thr = 0x21; aad_pdata->b_c_btn_thr = 0x21;
if (of_property_read_u32(aad_np, "dlg,c-mic-btn-thr", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,c-mic-btn-thr", &fw_val32) >= 0)
aad_pdata->c_mic_btn_thr = (u8) of_val32; aad_pdata->c_mic_btn_thr = (u8) fw_val32;
else else
aad_pdata->c_mic_btn_thr = 0x3E; aad_pdata->c_mic_btn_thr = 0x3E;
if (of_property_read_u32(aad_np, "dlg,btn-avg", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,btn-avg", &fw_val32) >= 0)
aad_pdata->btn_avg = da7219_aad_of_btn_avg(codec, of_val32); aad_pdata->btn_avg = da7219_aad_fw_btn_avg(codec, fw_val32);
else else
aad_pdata->btn_avg = DA7219_AAD_BTN_AVG_2; aad_pdata->btn_avg = DA7219_AAD_BTN_AVG_2;
if (of_property_read_u32(aad_np, "dlg,adc-1bit-rpt", &of_val32) >= 0) if (fwnode_property_read_u32(aad_np, "dlg,adc-1bit-rpt", &fw_val32) >= 0)
aad_pdata->adc_1bit_rpt = aad_pdata->adc_1bit_rpt =
da7219_aad_of_adc_1bit_rpt(codec, of_val32); da7219_aad_fw_adc_1bit_rpt(codec, fw_val32);
else else
aad_pdata->adc_1bit_rpt = DA7219_AAD_ADC_1BIT_RPT_1; aad_pdata->adc_1bit_rpt = DA7219_AAD_ADC_1BIT_RPT_1;
out:
of_node_put(aad_np);
return aad_pdata; return aad_pdata;
} }
@@ -769,9 +768,9 @@ int da7219_aad_init(struct snd_soc_codec *codec)
da7219->aad = da7219_aad; da7219->aad = da7219_aad;
da7219_aad->codec = codec; da7219_aad->codec = codec;
/* Handle any DT/platform data */ /* Handle any DT/ACPI/platform data */
if ((codec->dev->of_node) && (da7219->pdata)) if (da7219->pdata && !da7219->pdata->aad_pdata)
da7219->pdata->aad_pdata = da7219_aad_of_to_pdata(codec); da7219->pdata->aad_pdata = da7219_aad_fw_to_pdata(codec);
da7219_aad_handle_pdata(codec); da7219_aad_handle_pdata(codec);

32
sound/soc/codecs/da7219.c
View File

@@ -15,6 +15,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/property.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/pm.h> #include <linux/pm.h>
@@ -1418,7 +1419,7 @@ static struct snd_soc_dai_driver da7219_dai = {
/* /*
* DT * DT/ACPI
*/ */
static const struct of_device_id da7219_of_match[] = { static const struct of_device_id da7219_of_match[] = {
@@ -1434,7 +1435,7 @@ static const struct acpi_device_id da7219_acpi_match[] = {
MODULE_DEVICE_TABLE(acpi, da7219_acpi_match); MODULE_DEVICE_TABLE(acpi, da7219_acpi_match);
static enum da7219_micbias_voltage static enum da7219_micbias_voltage
da7219_of_micbias_lvl(struct snd_soc_codec *codec, u32 val) da7219_fw_micbias_lvl(struct device *dev, u32 val)
{ {
switch (val) { switch (val) {
case 1600: case 1600:
@@ -1450,13 +1451,13 @@ static enum da7219_micbias_voltage
case 2600: case 2600:
return DA7219_MICBIAS_2_6V; return DA7219_MICBIAS_2_6V;
default: default:
dev_warn(codec->dev, "Invalid micbias level"); dev_warn(dev, "Invalid micbias level");
return DA7219_MICBIAS_2_2V; return DA7219_MICBIAS_2_2V;
} }
} }
static enum da7219_mic_amp_in_sel static enum da7219_mic_amp_in_sel
da7219_of_mic_amp_in_sel(struct snd_soc_codec *codec, const char *str) da7219_fw_mic_amp_in_sel(struct device *dev, const char *str)
{ {
if (!strcmp(str, "diff")) { if (!strcmp(str, "diff")) {
return DA7219_MIC_AMP_IN_SEL_DIFF; return DA7219_MIC_AMP_IN_SEL_DIFF;
@@ -1465,29 +1466,29 @@ static enum da7219_mic_amp_in_sel
} else if (!strcmp(str, "se_n")) { } else if (!strcmp(str, "se_n")) {
return DA7219_MIC_AMP_IN_SEL_SE_N; return DA7219_MIC_AMP_IN_SEL_SE_N;
} else { } else {
dev_warn(codec->dev, "Invalid mic input type selection"); dev_warn(dev, "Invalid mic input type selection");
return DA7219_MIC_AMP_IN_SEL_DIFF; return DA7219_MIC_AMP_IN_SEL_DIFF;
} }
} }
static struct da7219_pdata *da7219_of_to_pdata(struct snd_soc_codec *codec) static struct da7219_pdata *da7219_fw_to_pdata(struct snd_soc_codec *codec)
{ {
struct device_node *np = codec->dev->of_node; struct device *dev = codec->dev;
struct da7219_pdata *pdata; struct da7219_pdata *pdata;
const char *of_str; const char *of_str;
u32 of_val32; u32 of_val32;
pdata = devm_kzalloc(codec->dev, sizeof(*pdata), GFP_KERNEL); pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata) if (!pdata)
return NULL; return NULL;
if (of_property_read_u32(np, "dlg,micbias-lvl", &of_val32) >= 0) if (device_property_read_u32(dev, "dlg,micbias-lvl", &of_val32) >= 0)
pdata->micbias_lvl = da7219_of_micbias_lvl(codec, of_val32); pdata->micbias_lvl = da7219_fw_micbias_lvl(dev, of_val32);
else else
pdata->micbias_lvl = DA7219_MICBIAS_2_2V; pdata->micbias_lvl = DA7219_MICBIAS_2_2V;
if (!of_property_read_string(np, "dlg,mic-amp-in-sel", &of_str)) if (!device_property_read_string(dev, "dlg,mic-amp-in-sel", &of_str))
pdata->mic_amp_in_sel = da7219_of_mic_amp_in_sel(codec, of_str); pdata->mic_amp_in_sel = da7219_fw_mic_amp_in_sel(dev, of_str);
else else
pdata->mic_amp_in_sel = DA7219_MIC_AMP_IN_SEL_DIFF; pdata->mic_amp_in_sel = DA7219_MIC_AMP_IN_SEL_DIFF;
@@ -1662,11 +1663,10 @@ static int da7219_probe(struct snd_soc_codec *codec)
break; break;
} }
/* Handle DT/Platform data */ /* Handle DT/ACPI/Platform data */
if (codec->dev->of_node)
da7219->pdata = da7219_of_to_pdata(codec);
else
da7219->pdata = dev_get_platdata(codec->dev); da7219->pdata = dev_get_platdata(codec->dev);
if (!da7219->pdata)
da7219->pdata = da7219_fw_to_pdata(codec);
da7219_handle_pdata(codec); da7219_handle_pdata(codec);

9
sound/soc/davinci/davinci-mcasp.c
View File

@@ -1599,7 +1599,14 @@ static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
pdata = pdev->dev.platform_data; pdata = pdev->dev.platform_data;
return pdata; return pdata;
} else if (match) { } else if (match) {
pdata = (struct davinci_mcasp_pdata*) match->data; pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
GFP_KERNEL);
if (!pdata) {
dev_err(&pdev->dev,
"Failed to allocate memory for pdata\n");
ret = -ENOMEM;
return pdata;
}
} else { } else {
/* control shouldn't reach here. something is wrong */ /* control shouldn't reach here. something is wrong */
ret = -EINVAL; ret = -EINVAL;