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arm64: dts: rockchip: rk3588: Adjust the HDMI DDC IO driver strength

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There is a bug in the HDMI controller DDC. The falling edge of
SDA and SCL almost coincide and cannot be adjusted, resulting
in poor compatibility of DDC. The compatibility of DDC can be
improved by increasing the driver strength of SCL and decreasing
the driver strength of SDA to increase the slope of the falling edge.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia7e70c3a8f7f3ee5e36f401919e36d045448250c
This commit is contained in:
Algea Cao
2022-08-30 15:31:22 +08:00
committed by Tao Huang
parent 419f401148
commit 3690970c81
2 changed files with 45 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
View File

@@ -578,14 +578,14 @@
hdmim0_tx0_scl: hdmim0-tx0-scl {
rockchip,pins =
/* hdmim0_tx0_scl */
<4 RK_PB7 5 &pcfg_pull_none_smt>;
<4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim0_tx0_sda: hdmim0-tx0-sda {
rockchip,pins =
/* hdmim0_tx0_sda */
<4 RK_PC0 5 &pcfg_pull_none_smt>;
<4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@@ -654,14 +654,14 @@
hdmim1_tx0_scl: hdmim1-tx0-scl {
rockchip,pins =
/* hdmim1_tx0_scl */
<0 RK_PD5 11 &pcfg_pull_none_smt>;
<0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx0_sda: hdmim1-tx0-sda {
rockchip,pins =
/* hdmim1_tx0_sda */
<0 RK_PD4 11 &pcfg_pull_none_smt>;
<0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@@ -682,14 +682,14 @@
hdmim1_tx1_scl: hdmim1-tx1-scl {
rockchip,pins =
/* hdmim1_tx1_scl */
<3 RK_PC6 5 &pcfg_pull_none_smt>;
<3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx1_sda: hdmim1-tx1-sda {
rockchip,pins =
/* hdmim1_tx1_sda */
<3 RK_PC5 5 &pcfg_pull_none_smt>;
<3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
hdmim2_rx_cec: hdmim2-rx-cec {
@@ -723,14 +723,14 @@
hdmim2_tx0_scl: hdmim2-tx0-scl {
rockchip,pins =
/* hdmim2_tx0_scl */
<3 RK_PC7 5 &pcfg_pull_none_smt>;
<3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx0_sda: hdmim2-tx0-sda {
rockchip,pins =
/* hdmim2_tx0_sda */
<3 RK_PD0 5 &pcfg_pull_none_smt>;
<3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@@ -744,14 +744,14 @@
hdmim2_tx1_scl: hdmim2-tx1-scl {
rockchip,pins =
/* hdmim2_tx1_scl */
<1 RK_PA4 5 &pcfg_pull_none_smt>;
<1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx1_sda: hdmim2-tx1-sda {
rockchip,pins =
/* hdmim2_tx1_sda */
<1 RK_PA3 5 &pcfg_pull_none_smt>;
<1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/

35
arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
View File

@@ -333,6 +333,41 @@
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
bias-disable;
drive-strength = <1>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
bias-disable;
drive-strength = <2>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
bias-disable;
drive-strength = <3>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
bias-disable;
drive-strength = <4>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
bias-disable;
drive-strength = <5>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_output_high: pcfg-output-high {
output-high;