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arm64: dts: mediatek: Format mediatek,larbs as an array of phandles

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Commit 39bd2b6a37 ("dt-bindings: Improve phandle-array schemas")
updated the mediatek,larbs property in the mediatek,iommu.yaml
dt-binding to make it clearer that the phandles passed to the property
are independent, rather than subsequent arguments to the first phandle.

Update the mediatek,larbs property in the arm64 Devicetrees to use the
same formatting. This change doesn't impact any behavior: the compiled
dtb is exactly the same. It does however fix the warnings generated by
dtbs_check.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220301203147.1143782-2-nfraprado@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Nícolas F. R. A. Prado
2022-03-01 15:31:47 -05:00
committed by Matthias Brugger
parent 3123109284
commit 33c7874b44
4 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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@@ -329,8 +329,8 @@
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>; clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk"; clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
&larb3 &larb6>; <&larb3>, <&larb6>;
#iommu-cells = <1>; #iommu-cells = <1>;
}; };
@@ -346,7 +346,7 @@
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>; clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk"; clock-names = "bclk";
mediatek,larbs = <&larb4 &larb5 &larb7>; mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
#iommu-cells = <1>; #iommu-cells = <1>;
}; };

2
arch/arm64/boot/dts/mediatek/mt8167.dtsi
View File

@@ -174,7 +174,7 @@
iommu: m4u@10203000 { iommu: m4u@10203000 {
compatible = "mediatek,mt8167-m4u"; compatible = "mediatek,mt8167-m4u";
reg = <0 0x10203000 0 0x1000>; reg = <0 0x10203000 0 0x1000>;
mediatek,larbs = <&larb0 &larb1 &larb2>; mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
#iommu-cells = <1>; #iommu-cells = <1>;
}; };

4
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@@ -588,8 +588,8 @@
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>; clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk"; clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
&larb3 &larb4 &larb5>; <&larb3>, <&larb4>, <&larb5>;
#iommu-cells = <1>; #iommu-cells = <1>;
}; };

4
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@@ -682,8 +682,8 @@
compatible = "mediatek,mt8183-m4u"; compatible = "mediatek,mt8183-m4u";
reg = <0 0x10205000 0 0x1000>; reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
&larb4 &larb5 &larb6>; <&larb4>, <&larb5>, <&larb6>;
#iommu-cells = <1>; #iommu-cells = <1>;
}; };