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clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs

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On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence.  Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Andrew Bresticker
2015-06-18 17:28:40 -04:00
committed by Thierry Reding
parent f55532a0c0
commit 3358d2d9f4
2 changed files with 63 additions and 0 deletions
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5
include/linux/clk/tegra.h
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@@ -121,4 +121,9 @@ static inline void tegra_cpu_clock_resume(void)
}
#endif
extern void tegra210_xusb_pll_hw_control_enable(void);
extern void tegra210_xusb_pll_hw_sequence_start(void);
extern void tegra210_sata_pll_hw_control_enable(void);
extern void tegra210_sata_pll_hw_sequence_start(void);
#endif /* __LINUX_CLK_TEGRA_H_ */