Merge tag 'perf-urgent-2023-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Thomas Gleixner:
"A small set of perf fixes:
- Make the MSR-readout based CHA discovery work around broken
discovery tables in some SPR firmwares.
- Prevent saving PEBS configuration which has software bits set that
cause a crash when restored into the relevant MSR"
* tag 'perf-urgent-2023-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/uncore: Correct the number of CHAs on SPR
perf/x86/intel: Save/restore cpuc->active_pebs_data_cfg when using guest PEBS
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@@ -4074,7 +4074,7 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
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if (x86_pmu.intel_cap.pebs_baseline) {
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arr[(*nr)++] = (struct perf_guest_switch_msr){
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.msr = MSR_PEBS_DATA_CFG,
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.host = cpuc->pebs_data_cfg,
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.host = cpuc->active_pebs_data_cfg,
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.guest = kvm_pmu->pebs_data_cfg,
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};
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}
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@@ -6150,6 +6150,7 @@ static struct intel_uncore_type spr_uncore_mdf = {
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};
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#define UNCORE_SPR_NUM_UNCORE_TYPES 12
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#define UNCORE_SPR_CHA 0
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#define UNCORE_SPR_IIO 1
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#define UNCORE_SPR_IMC 6
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#define UNCORE_SPR_UPI 8
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@@ -6460,12 +6461,22 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
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return max + 1;
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}
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#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
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void spr_uncore_cpu_init(void)
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{
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struct intel_uncore_type *type;
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u64 num_cbo;
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uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
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UNCORE_SPR_MSR_EXTRA_UNCORES,
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spr_msr_uncores);
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type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
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if (type) {
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rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
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type->num_boxes = num_cbo;
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}
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spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
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}
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