Merge tag 'mmc-updates-for-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc
Pull MMC updates from Chris Ball:
"MMC highlights for 3.8:
Core:
- Expose access to the eMMC RPMB ("Replay Protected Memory Block")
area by extending the existing mmc_block ioctl.
- Add SDIO powered-suspend DT properties to the core MMC DT binding.
- Add no-1-8-v DT flag for boards where the SD controller reports
that it supports 1.8V but the board itself has no way to switch to
1.8V.
- More work on switching to 1.8V UHS support using a vqmmc regulator.
- Fix up a case where the slot-gpio helper may fail to reset the host
controller properly if a card was removed during a transfer.
- Fix several cases where a broken device could cause an infinite
loop while we wait for a register to update.
Drivers:
- at91-mci: Remove obsolete driver, atmel-mci handles these devices
now.
- sdhci-dove: Allow using GPIOs for card-detect notifications.
- sdhci-esdhc: Fix for recovering from ADMA errors on broken silicon.
- sdhci-s3c: Add pinctrl support.
- wmt-sdmmc: New driver for WonderMedia SD/MMC controllers."
* tag 'mmc-updates-for-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: (65 commits)
mmc: sdhci: implement the .card_event() method
mmc: extend the slot-gpio card-detection to use host's .card_event() method
mmc: add a card-event host operation
mmc: sdhci-s3c: Fix compilation warning
mmc: sdhci-pci: Enable SDHCI_CAN_DO_HISPD for Ricoh SDHCI controller
mmc: sdhci-dove: allow GPIOs to be used for card detection on Dove
mmc: sdhci-dove: use two-stage initialization for sdhci-pltfm
mmc: sdhci-dove: use devm_clk_get()
mmc: eSDHC: Recover from ADMA errors
mmc: dw_mmc: remove duplicated buswidth code
mmc: dw_mmc: relocate where dw_mci_setup_bus() is called from
mmc: Limit MMC speed to 52MHz if not HS200
mmc: dw_mmc: use devres functions in dw_mmc
mmc: sh_mmcif: remove unneeded clock connection ID
mmc: sh_mobile_sdhi: remove unneeded clock connection ID
mmc: sh_mobile_sdhi: fix clock frequency printing
mmc: Remove redundant null check before kfree in bus.c
mmc: Remove redundant null check before kfree in sdio_bus.c
mmc: sdhci-imx-esdhc: use more devm_* functions
mmc: dt: add no-1-8-v device tree flag
...
This commit is contained in:
@@ -85,6 +85,7 @@ struct mmc_ext_csd {
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bool boot_ro_lockable;
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u8 raw_exception_status; /* 53 */
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u8 raw_partition_support; /* 160 */
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u8 raw_rpmb_size_mult; /* 168 */
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u8 raw_erased_mem_count; /* 181 */
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u8 raw_ext_csd_structure; /* 194 */
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u8 raw_card_type; /* 196 */
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@@ -206,6 +207,7 @@ struct mmc_part {
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#define MMC_BLK_DATA_AREA_MAIN (1<<0)
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#define MMC_BLK_DATA_AREA_BOOT (1<<1)
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#define MMC_BLK_DATA_AREA_GP (1<<2)
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#define MMC_BLK_DATA_AREA_RPMB (1<<3)
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};
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/*
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@@ -170,6 +170,8 @@ extern int mmc_erase_group_aligned(struct mmc_card *card, unsigned int from,
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extern unsigned int mmc_calc_max_discard(struct mmc_card *card);
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extern int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen);
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extern int mmc_set_blockcount(struct mmc_card *card, unsigned int blockcount,
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bool is_rel_write);
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extern int mmc_hw_reset(struct mmc_host *host);
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extern int mmc_hw_reset_check(struct mmc_host *host);
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extern int mmc_can_reset(struct mmc_card *card);
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@@ -229,8 +229,9 @@ struct dw_mci_board {
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u32 quirks; /* Workaround / Quirk flags */
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unsigned int bus_hz; /* Clock speed at the cclk_in pad */
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unsigned int caps; /* Capabilities */
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unsigned int caps2; /* More capabilities */
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u32 caps; /* Capabilities */
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u32 caps2; /* More capabilities */
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u32 pm_caps; /* PM capabilities */
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/*
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* Override fifo depth. If 0, autodetect it from the FIFOTH register,
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* but note that this may not be reliable after a bootloader has used
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@@ -53,12 +53,12 @@ struct mmc_ios {
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#define MMC_TIMING_LEGACY 0
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#define MMC_TIMING_MMC_HS 1
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#define MMC_TIMING_SD_HS 2
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#define MMC_TIMING_UHS_SDR12 MMC_TIMING_LEGACY
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#define MMC_TIMING_UHS_SDR25 MMC_TIMING_SD_HS
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#define MMC_TIMING_UHS_SDR50 3
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#define MMC_TIMING_UHS_SDR104 4
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#define MMC_TIMING_UHS_DDR50 5
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#define MMC_TIMING_MMC_HS200 6
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#define MMC_TIMING_UHS_SDR12 3
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#define MMC_TIMING_UHS_SDR25 4
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#define MMC_TIMING_UHS_SDR50 5
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#define MMC_TIMING_UHS_SDR104 6
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#define MMC_TIMING_UHS_DDR50 7
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#define MMC_TIMING_MMC_HS200 8
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#define MMC_SDR_MODE 0
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#define MMC_1_2V_DDR_MODE 1
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@@ -136,6 +136,7 @@ struct mmc_host_ops {
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void (*enable_preset_value)(struct mmc_host *host, bool enable);
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int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv);
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void (*hw_reset)(struct mmc_host *host);
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void (*card_event)(struct mmc_host *host);
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};
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struct mmc_card;
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@@ -211,7 +212,7 @@ struct mmc_host {
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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unsigned long caps; /* Host capabilities */
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u32 caps; /* Host capabilities */
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#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
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#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
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@@ -241,7 +242,7 @@ struct mmc_host {
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#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
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#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
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unsigned int caps2; /* More host capabilities */
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u32 caps2; /* More host capabilities */
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#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
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#define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */
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@@ -286,6 +286,7 @@ struct _mmc_csd {
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#define EXT_CSD_BKOPS_START 164 /* W */
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#define EXT_CSD_SANITIZE_START 165 /* W */
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#define EXT_CSD_WR_REL_PARAM 166 /* RO */
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#define EXT_CSD_RPMB_MULT 168 /* RO */
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#define EXT_CSD_BOOT_WP 173 /* R/W */
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#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
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#define EXT_CSD_PART_CONFIG 179 /* R/W */
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@@ -339,6 +340,7 @@ struct _mmc_csd {
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#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
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#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
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#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
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#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
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#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
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@@ -1,19 +0,0 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_MMC_MXS_MMC_H__
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#define __LINUX_MMC_MXS_MMC_H__
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struct mxs_mmc_platform_data {
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int wp_gpio; /* write protect pin */
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unsigned int flags;
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#define SLOTF_4_BIT_CAPABLE (1 << 0)
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#define SLOTF_8_BIT_CAPABLE (1 << 1)
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};
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#endif /* __LINUX_MMC_MXS_MMC_H__ */
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@@ -92,6 +92,8 @@ struct sdhci_host {
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#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
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#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
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/* The system physically doesn't support 1.8v, even if the host does */
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#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
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int irq; /* Device IRQ */
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void __iomem *ioaddr; /* Mapped address */
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@@ -158,8 +160,8 @@ struct sdhci_host {
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struct timer_list timer; /* Timer for timeouts */
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unsigned int caps; /* Alternative CAPABILITY_0 */
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unsigned int caps1; /* Alternative CAPABILITY_1 */
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u32 caps; /* Alternative CAPABILITY_0 */
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u32 caps1; /* Alternative CAPABILITY_1 */
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unsigned int ocr_avail_sdio; /* OCR bit masks */
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unsigned int ocr_avail_sd;
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@@ -38,6 +38,7 @@
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* @max_speed: the maximum speed supported
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* @host_caps: Standard MMC host capabilities bit field.
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* @quirks: quirks of platfrom
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* @quirks2: quirks2 of platfrom
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* @pm_caps: pm_caps of platfrom
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*/
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struct sdhci_pxa_platdata {
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@@ -48,9 +49,10 @@ struct sdhci_pxa_platdata {
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unsigned int ext_cd_gpio;
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bool ext_cd_gpio_invert;
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unsigned int max_speed;
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unsigned int host_caps;
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unsigned int host_caps2;
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u32 host_caps;
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u32 host_caps2;
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unsigned int quirks;
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unsigned int quirks2;
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unsigned int pm_caps;
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};
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