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arm64: dts: rockchip: rk3568: rename mipi_dphy to video_phy

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Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ie019c9d27e06328d45920d41c0a065f8bc47588f
This commit is contained in:
Guochun Huang
2021-06-24 18:14:17 +08:00
committed by Tao Huang
parent a4bbfc35fd
commit 0f20a27adc
23 changed files with 76 additions and 97 deletions
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4
arch/arm64/boot/dts/rockchip/rk3566-box.dtsi
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@@ -239,11 +239,11 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "okay"; status = "okay";
}; };

8
arch/arm64/boot/dts/rockchip/rk3566-evb-mipitest-v10.dtsi
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@@ -156,7 +156,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -179,7 +179,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -322,11 +322,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

8
arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10-lvds.dts
View File

@@ -97,11 +97,3 @@
status = "okay"; status = "okay";
connect = <&vp1_out_lvds>; connect = <&vp1_out_lvds>;
}; };
&mipi_dphy0 {
status = "disabled";
};
&mipi_dphy1 {
status = "disabled";
};

8
arch/arm64/boot/dts/rockchip/rk3566-evb1-ddr4-v10.dtsi
View File

@@ -156,7 +156,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -179,7 +179,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -317,11 +317,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10-eink.dts
View File

@@ -285,7 +285,7 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "disabled"; status = "disabled";
}; };

10
arch/arm64/boot/dts/rockchip/rk3566-evb2-lp4x-v10.dtsi
View File

@@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/pinctrl/rockchip.h>
#include "rk3566.dtsi" #include "rk3566.dtsi"
#include "rk3566-evb.dtsi" #include "rk3566-evb.dtsi"
@@ -167,7 +168,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -190,7 +191,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -406,11 +407,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };
@@ -592,4 +593,3 @@
BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };

8
arch/arm64/boot/dts/rockchip/rk3566-evb3-ddr3-v10.dtsi
View File

@@ -88,7 +88,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -111,7 +111,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -283,11 +283,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

8
arch/arm64/boot/dts/rockchip/rk3566-evb5-lp4x-v10.dtsi
View File

@@ -67,7 +67,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -91,7 +91,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -180,11 +180,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w103.dts
View File

@@ -857,7 +857,7 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink-w6.dts
View File

@@ -697,7 +697,7 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-rk817-eink.dts
View File

@@ -713,7 +713,7 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-k108.dts
View File

@@ -990,7 +990,7 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };

4
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-rkg11.dts
View File

@@ -892,11 +892,11 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "okay"; status = "okay";
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet-v10.dts
View File

@@ -918,7 +918,7 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };

2
arch/arm64/boot/dts/rockchip/rk3566-rk817-tablet.dts
View File

@@ -917,7 +917,7 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };

8
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10.dtsi
View File

@@ -152,7 +152,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -172,7 +172,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -353,11 +353,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dts
View File

@@ -45,7 +45,7 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "disabled"; status = "disabled";
}; };

8
arch/arm64/boot/dts/rockchip/rk3568-evb2-lp4x-v10.dtsi
View File

@@ -98,7 +98,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -118,7 +118,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -235,11 +235,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

8
arch/arm64/boot/dts/rockchip/rk3568-evb5-ddr4-v10.dtsi
View File

@@ -165,7 +165,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -185,7 +185,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -397,11 +397,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

2
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts
View File

@@ -24,7 +24,7 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "disabled"; status = "disabled";
}; };

8
arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10.dtsi
View File

@@ -109,7 +109,7 @@
}; };
/* /*
* mipi_dphy0 needs to be enabled * video_phy0 needs to be enabled
* when dsi0 is enabled * when dsi0 is enabled
*/ */
&dsi0 { &dsi0 {
@@ -129,7 +129,7 @@
}; };
/* /*
* mipi_dphy1 needs to be enabled * video_phy1 needs to be enabled
* when dsi1 is enabled * when dsi1 is enabled
*/ */
&dsi1 { &dsi1 {
@@ -319,11 +319,11 @@
}; };
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };

4
arch/arm64/boot/dts/rockchip/rk3568-nvr.dtsi
View File

@@ -295,11 +295,11 @@
status = "okay"; status = "okay";
}; };
&mipi_dphy0 { &video_phy0 {
status = "okay"; status = "okay";
}; };
&mipi_dphy1 { &video_phy1 {
status = "okay"; status = "okay";
}; };

61
arch/arm64/boot/dts/rockchip/rk3568.dtsi
View File

@@ -1799,12 +1799,12 @@
compatible = "rockchip,rk3568-mipi-dsi"; compatible = "rockchip,rk3568-mipi-dsi";
reg = <0x0 0xfe060000 0x0 0x10000>; reg = <0x0 0xfe060000 0x0 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&mipi_dphy0>; clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
clock-names = "pclk", "hclk", "hs_clk"; clock-names = "pclk", "hclk";
resets = <&cru SRST_P_DSITX_0>; resets = <&cru SRST_P_DSITX_0>;
reset-names = "apb"; reset-names = "apb";
phys = <&mipi_dphy0>; phys = <&video_phy0>;
phy-names = "mipi_dphy"; phy-names = "dphy";
power-domains = <&power RK3568_PD_VO>; power-domains = <&power RK3568_PD_VO>;
rockchip,grf = <&grf>; rockchip,grf = <&grf>;
#address-cells = <1>; #address-cells = <1>;
@@ -1837,12 +1837,12 @@
compatible = "rockchip,rk3568-mipi-dsi"; compatible = "rockchip,rk3568-mipi-dsi";
reg = <0x0 0xfe070000 0x0 0x10000>; reg = <0x0 0xfe070000 0x0 0x10000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&mipi_dphy1>; clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
clock-names = "pclk", "hclk", "hs_clk"; clock-names = "pclk", "hclk";
resets = <&cru SRST_P_DSITX_1>; resets = <&cru SRST_P_DSITX_1>;
reset-names = "apb"; reset-names = "apb";
phys = <&mipi_dphy1>; phys = <&video_phy1>;
phy-names = "mipi_dphy"; phy-names = "dphy";
power-domains = <&power RK3568_PD_VO>; power-domains = <&power RK3568_PD_VO>;
rockchip,grf = <&grf>; rockchip,grf = <&grf>;
#address-cells = <1>; #address-cells = <1>;
@@ -3259,48 +3259,35 @@
status = "disabled"; status = "disabled";
}; };
mipi_dphy0: mipi-dphy@fe850000 { video_phy0: phy@fe850000 {
compatible = "rockchip,rk3568-mipi-dphy"; compatible = "rockchip,rk3568-dsi-dphy";
reg = <0x0 0xfe850000 0x0 0x10000>; reg = <0x0 0xfe850000 0x0 0x10000>,
clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; <0x0 0xfe060000 0x0 0x10000>;
clock-names = "ref", "pclk"; reg-names = "phy", "host";
clock-output-names = "mipi_dphy_pll"; clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
<&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
clock-names = "ref", "pclk", "pclk_host";
#clock-cells = <0>; #clock-cells = <0>;
resets = <&cru SRST_P_MIPIDSIPHY0>; resets = <&cru SRST_P_MIPIDSIPHY0>;
reset-names = "apb"; reset-names = "apb";
power-domains = <&power RK3568_PD_VO>; power-domains = <&power RK3568_PD_VO>;
#phy-cells = <0>; #phy-cells = <0>;
rockchip,grf = <&grf>;
status = "disabled"; status = "disabled";
}; };
video_phy0: video-phy@fe850000 { video_phy1: phy@fe860000 {
compatible = "rockchip,rk3568-video-phy"; compatible = "rockchip,rk3568-dsi-dphy";
reg = <0x0 0xfe850000 0x0 0x10000>, reg = <0x0 0xfe860000 0x0 0x10000>,
<0x0 0xfe060000 0x0 0x10000>; <0x0 0xfe070000 0x0 0x10000>;
clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, reg-names = "phy", "host";
<&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
clock-names = "ref", "pclk_phy", "pclk_host"; <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
#clock-cells = <0>; clock-names = "ref", "pclk", "pclk_host";
resets = <&cru SRST_P_MIPIDSIPHY0>;
reset-names = "rst";
power-domains = <&power RK3568_PD_VO>;
#phy-cells = <0>;
status = "disabled";
};
mipi_dphy1: mipi-dphy@fe860000 {
compatible = "rockchip,rk3568-mipi-dphy";
reg = <0x0 0xfe860000 0x0 0x10000>;
clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
clock-names = "ref", "pclk";
clock-output-names = "mipi_dphy1_pll";
#clock-cells = <0>; #clock-cells = <0>;
resets = <&cru SRST_P_MIPIDSIPHY1>; resets = <&cru SRST_P_MIPIDSIPHY1>;
reset-names = "apb"; reset-names = "apb";
power-domains = <&power RK3568_PD_VO>; power-domains = <&power RK3568_PD_VO>;
#phy-cells = <0>; #phy-cells = <0>;
rockchip,grf = <&grf>;
status = "disabled"; status = "disabled";
}; };